Arm Bus Error
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Linux Lshw Bus Error
hiring developers or posting ads with us Stack Overflow Questions Jobs Documentation Tags Users Badges Ask Question x Dismiss bus error in qt embedded Join the Stack Overflow Community Stack Overflow is a community of 4.7 million programmers, just like you, helping each other. Join them; it only takes a minute: Sign up What is a bus lshw network bus error error? up vote 154 down vote favorite 49 What does the "bus error" message mean, and how does it differ from a segfault? c unix segmentation-fault bus-error share|improve this question edited Oct 18 '15 at 10:44 Cool Guy 15.8k51952 asked Oct 17 '08 at 14:48 raldi 7,226216178 add a comment| 15 Answers 15 active oldest votes up vote 149 down vote accepted Bus errors are
Btsync Bus Error
rare nowadays on x86 and occur when your processor cannot even attempt the memory access requested, typically: using a processor instruction with an address that does not satisfy its alignment requirements. Segmentation faults occur when accessing memory which does not belong to your process, they are very common and are typically the result of: using a pointer to something that was deallocated. using an uninitialized hence bogus pointer. using a null pointer. overflowing a buffer. PS: To be more precise this is not manipulating the pointer itself that will cause issues, it's accessing the memory it points to (dereferencing). share|improve this answer edited Oct 17 '08 at 15:18 answered Oct 17 '08 at 15:12 bltxd 5,68322336 52 They aren't rare; I'm just at Exercise 9 from How to Learn C the Hard Way and already encountered one... –11684 Mar 26 '13 at 20:12 5 Another cause of bus errors (on Linux anyway) is when the operating system can't back a virtual page with physical memory (e.g. low-memory conditions or out of huge pages when using huge page memory.) Typically mmap (and malloc) just reserve the virtual address space, and the kerne
challenged and removed. (July 2015) (Learn how and when to remove this template message) In computing, a bus error is a fault raised by hardware, notifying an operating system (OS) that a process is trying to access linux embedded arm memory that the CPU cannot physically address: an invalid address for the address bus, arm bus fault hence the name. In modern use on most architectures these are much rarer than segmentation faults, which occur primarily due to
Arm Bus Architecture
memory access violations: problems in the logical address or permissions. On POSIX-compliant platforms, bus errors usually result in the SIGBUS signal being sent to the process that caused the error. SIGBUS can also be caused http://stackoverflow.com/questions/212466/what-is-a-bus-error by any general device fault that the computer detects, though a bus error rarely means that the computer hardware is physically broken—it is normally caused by a bug in a program's source code.[citation needed] Bus errors may also be raised for certain other paging errors; see below. Contents 1 Causes 1.1 Non-existent address 1.2 Unaligned access 1.3 Paging errors 2 Example 3 References Causes[edit] There are at least three https://en.wikipedia.org/wiki/Bus_error main causes of bus errors: Non-existent address[edit] Software instructs the CPU to read or write a specific physical memory address. Accordingly, the CPU sets this physical address on its address bus and requests all other hardware connected to the CPU to respond with the results, if they answer for this specific address. If no other hardware responds, the CPU raises an exception, stating that the requested physical address is unrecognized by the whole computer system. Note that this only covers physical memory addresses. Trying to access an undefined virtual memory address is generally considered to be a segmentation fault rather than a bus error, though if the MMU is separate, the processor can't tell the difference. Unaligned access[edit] Most CPUs are byte-addressable, where each unique memory address refers to an 8-bit byte. Most CPUs can access individual bytes from each memory address, but they generally cannot access larger units (16 bits, 32 bits, 64 bits and so on) without these units being "aligned" to a specific boundary (the x86 platform being a notable exception). For example, if multi-byte accesses must be 16 bit-aligned, addresses (given in bytes) at 0, 2, 4, 6, and so on would be considered aligned and therefore accessible, while addresses 1, 3, 5
sorted by: [ date ] [ thread ] [ subject ] [ author ] On Thu, Nov 05, 2015 at 05:25:14PM +0100, Gilles Chanteperdrix wrote: > I am sure. Xenomai does not http://www.xenomai.org/pipermail/xenomai/2015-November/035392.html use H_DMA on armv7, so, it is not used > if your code, https://gcc.gnu.org/ml/gcc/2015-05/msg00149.html it is not used at all. Well we are using it for one allocation for talking to a network port. If I remove it, I get a NULL pointer dereference, so it clearly matters to something in our code. > > It does appear that when LPAE is enabled H_DMA does do something on bus error arm, > > but only when LPAE is enabled since that enables ZONE_DMA. > > I never said that H_DMA did nothing. OK I misunderstood then. Setting /proc/cpu/alignment to 0 gives the kernel message: alignment: ignoring faults is unsafe on this CPU. Defaulting to fixup mode. Apparently armv6+ with CR_U set is not allowed to turn off fixups. The fixups don't work for the xenomai code though it arm bus error would seem. I get: Alignment trap: not handling instruction f8d03002 at [<00020be0>] Unhandled fault: alignment exception (0x221) at 0xb56ba006 Code looks like this: 20bd8: 6802 ldr r2, [r0, #0] 20bda: 680b ldr r3, [r1, #0] 20bdc: 429a cmp r2, r3 20bde: d107 bne.n 20bf0 <_ZNK11rc_mac_addreqERKS_+0x18> -> 20be0: f8d0 3002 ldr.w r3, [r0, #2] 20be4: f8d1 0002 ldr.w r0, [r1, #2] 20be8: 1a1b subs r3, r3, r0 20bea: 4258 negs r0, r3 20bec: 4158 adcs r0, r3 20bee: 4770 bx lr 20bf0: 2000 movs r0, #0 20bf2: 4770 bx lr As far as I understand it, ldr.w should work for unaligned reads as long as the page if flagged normal. Still trying to determine what the page is marked as in this case. And looking at the code compiled with gcc-4.6 it is obviously different and would not have alignment issues (but is much less efficient): 49a46: b5f0 push {r4, r5, r6, r7, lr} 49a48: 7847 ldrb r7, [r0, #1] 49a4a: 7803 ldrb r3, [r0, #0] 49a4c: 784e ldrb r6, [r1, #1] 49a4e: ea43 2707 orr.w r7, r3, r7, lsl #8 49a52: 780b ldrb r3, [r1, #0] 49a54: 7884 ldrb r4, [r0, #2] 49a56: ea43 2606 orr.w r6, r3, r6, lsl #8 49