Error 10219 Verilog
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File(.v) contains the specified variable, which does not have a net type. However, only variables with a net type (wire, wand, etc.) may be assigned using continuous assignments. ACTION: Declare the specified variable with a net type, or assign it a value in a procedural statement such as an always construct. See also: Section 6.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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to a CPLD. To do that I need a bidirectional 8-bit bus. I thought I could declare the http://www.alteraforum.com/forum/archive/index.php/t-36371.html pins to be bidirectional and with a mux, read to or http://zhidao.baidu.com/question/191993129.html write from the pins as necessary. My Verilog code for the mux is: [code] always @(negedge clk) begin: TESTUSB_MUX if ((TXE == 0)) begin USBBUS <= OUTBUS; end else if ((RXF == 0)) begin INBUS <= USBBUS; end end [\code] But the Fitter generates errors, error 10219 e.g., Error: Can't reserve pin "USBBUS[0]" because its name already exists with a different direction How can a bidirectional bus be created? Gary RichardsonJune 19th, 2012, 12:18 PMI rewrote my code as: output [7:0] USBBUS; wire [7:0] USBBUS; reg [7:0] outbus; wire [7:0] inbus; always @(negedge clk) begin if ((TXE == 0)) begin USBBUS <= outbus; end error 10219 verilog else if ((RXF == 0)) begin inbus <= USBBUS; end else begin USBBUS <= 8'hz; end end Now my error is: Error (10137): Verilog HDL Procedural Assignment error at testUSB.v(344): object "USBBUS" on left-hand side of assignment must have a variable data type Any suggestions? rbugalhoJune 19th, 2012, 03:09 PMYou cannot use a "wire" in an "always" statement. It's a Verilog idiosyncranie. What people usually do, when dealing with bi-directional signals is to decompose it in 3 variants (input, output and output enable) like this. input wire [7:0] USBBUS; wire [7:0] USBBUS_i; reg [7:0] USBBUS_o; reg USBBUS_oe; assign USBBUS_i = USBBUS; assign USBBUS = USBBUS_oe == 1'b1 ? USBBUS_o : 8'hzz; always @ (negedge clk) begin if(write condition) begin USBBUS_o <= outbus; USBBUS_oe <= 1'b1; end else begin USBBUS_o <= 8'hxx; USBBUS_oe <= 1'b0; end if (read condition) begin inbus <= USBBUS_i; end end Gary RichardsonJune 19th, 2012, 06:24 PMThanks for your reply. I made the changes you suggested but now Quartus generates this error message: Error (102
知道日报 真相问答机 知道大数据 知道多世界 知道非遗 用户 知道芝麻 知道之星 芝麻将 芝麻团 知道行家 日报作者 机构合作 机构行家 开放平台 品牌合作 知道福利 财富商城 知道活动 特色 经验 问咖 宝宝知道 拇指医生 作业帮 手机版 我的知道 搜索答案 百度知道 >电脑/网络 >常见软件 verilog程序问题，还是quartus的问题？？ 今天我尝试在quartus中进行综合。所以我从书中抄了下面的verilog代码（很简单，很基础），(项目和文件名都为fre_ctr)： module fre_ctr(rst,clk,load,count_en,count_clr); output count_en,count_clr,load; input rst,clk; reg count_clr,load; alway... 今我尝试quartus进行综合所我书抄面verilog代码（简单基础）(项目文件名都fre_ctr)：module fre_ctr(rst,clk,load,count_en,count_clr);output count_en,count_clr,load;input rst,clk;reg count_clr,load;always @(posedge clk) begin if(rst) begin count_en <= 0; load <= 1; end else begin count_en <= ~count_en; load <= ~count_en; end endassign count_clr = ~clk&load;endmodule编译错：Error (10137): Verilog HDL Procedural Assignment error at fre_ctr.v(6): object "count_en" on left-hand side of assignment must have a variable data typeError (10137): Verilog HDL Procedural Assignment error at fre_ctr.v(7): object "count_en" on left-hand side of assignment must have a variable data typeError (10219): Verilog HDL Continuous Assignment error at fre_ctr.v(11): object "count_clr" on left-hand side of assignment must have a net type我知道我代码错哪希望家指点谢 展开 cheng_an12 2010-10-20 10:44 2010-10-20 15:12 最佳答案 呵呵object "count_clr" on left-hand side of assignment must have a net type意思assign语句能wire型变量赋值Error (10137): Verilog HDL Procedural Assignment error at fre_ctr.v(6): object "count_en" on left-hand side of assignment must have a variable data typealways块语句能reg型变量赋值问题两点~~看看书吧 本回答由网友推荐 评论 luochris2010 采纳率：41% 擅长： 其他编程语言 其他回答 程序第四行：reg count_clr,load;应该改reg count_en,load;always块面信号赋值信号类型定要reg型；always块外用assign语句型号赋值信号类型定wire型；程序count_clr output变量声明reg型导致第三error；没count_en声明称reg导致第二error；另外output缺省wire型 clingclear | 2010-10-26 13:17 评论 reg count_clr,load;这句话要改为wire count_clr;reg load