Error Module Or Primitive Not Defined
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what I am going to do with the following simulation error. Hi, all: I am wondering what I am going to do with the following simulation error. Best Regards, Leon ---------------------------------------------------> Compiling source file "tm.v" Compiling included source file "/home/leonle/gatelevel/stg1_ld_net.v" Continuing compilation of source file "tm.v" Scanning library directory "/tools/my_tech_liblog_lib/std_cells" Scanning library directory "/tools/my_tech_liblog_lib/std_cells" Error! Instance specific item not found in `uselib http://computer-programming-forum.com/41-verilog/611a40af85d1d2f2.htm path: Directory : /tools/my_tech_lib http://superuser.com/questions/1084121/ansible-most-simple-case-not-running-module-args-is-not-defined-error/1087681 log_lib/std_cells Libext : .v error module [Verilog-LISRE] "/tools/my_tech_liblog_lib/std _cells/dfcrb1.v",... Error! Instance specific item not found in `uselib path: Directory : /tools/my_tech_lib log_lib/std_cells error module or Libext : .v [Verilog-LISRE] "/tools/my_tech_liblog_lib/std _cells/dfcrq2.v",... Error! Module or primitive (U_FD_P_RB_NO) not defined [Verilog-MOPND] "/tools/my_tech_liblog_lib/std _cells/dfcrb1.v", 42: U_FD_P_RB_NO #(1) (buf_Q, D, CP, CDN, notifier); Error! Module or primitive (U_FD_P_RB_NO) not defined [Verilog-MOPND] "/tools/my_tech_liblog_lib/std _cells/dfcrq2.v", 42: U_FD_P_RB_NO #(1) (Q, D, CP, CDN, notifier); 4 errors End of VERILOG-XL 3.10.p001 Apr 27, 2001 09:45:39 Thu, 23 Oct 2003 16:08:01 GMT Srinivasan Venkataramana#2 / 2 I am wondering what I am going to do with the following simulation error. Hi, Error! Module or primitive (U_FD_P_RB_NO) not defined This means that there is a UDP (User Defined Primitive) (or a module, but likely it is an UDP) is UNDEFINED! Check the file: /tools/my_tech_liblog_lib/std_cells/dfcrb1.v Line number: 42 It should read like: U_FD_P_RB_NO #(1) (buf_Q, D, CP, CDN, notifier); And this "U_FD_P_RB_NO" is something that's not "visible" to the simulator/compiler. Essentially you are not properly giving the required standard cell libraries to Verilog-XL. Where did you get this library from? In some cases I have seen that the UDPs are put together in a separate file. So try and search for them in your library (Verilog library, provided by your ASIC Vendor). HTH, Srini Quote: > Hi, all: > I am
here for a quick overview of the site Help Center Detailed answers to any questions you might have Meta Discuss the workings and policies of this site About Us Learn more about Stack Overflow the company Business Learn more about hiring developers or posting ads with us Super User Questions Tags Users Badges Unanswered Ask Question _ Super User is a question and answer site for computer enthusiasts and power users. Join them; it only takes a minute: Sign up Here's how it works: Anybody can ask a question Anybody can answer The best answers are voted up and rise to the top ansible most simple case not running - “MODULE_ARGS is not defined” error up vote 1 down vote favorite 1 I'm trying to begin using ansible, so I am walking thru an introduction. I've installed ansible on Debian Jessie, using apt-get. It displays version 2.2 I've configured /etc/ansible/hosts file like this: test ansible_connection=local If I run ansible all -m ping I get an optimistic result: test | SUCCESS => { "changed": false, "ping": "pong" } But as I try (as intro suggests) running the most primitive command possible: ansible all -a "/bin/echo hello" I get a very disappointing An exception occurred during task execution. To see the full traceback, use -vvv. The error was: NameError: global name 'MODULE_ARGS' is not defined test | FAILED | rc=0 >> MODULE FAILURE As I run it with -vvv, I get Using /etc/ansible/ansible.cfg as config file Using module file /usr/share/ansible/commands/command