Error With Switch Core Bist Test Phase
IP isWhoisCalculatorTool PointsNewsNews tip?ForumsAll ForumsHot TopicsGalleryInfoHardwareAll FAQsSite FAQDSL FAQCable TechAboutcontactabout uscommunityISP FAQAdd ISPISP Ind. ForumsJoin Search similar:[HELP] 1751 intermittent connectivity w/Linux clients[Config] Me again. New router, no DSL link. A simple question this time.[HELP] Cisco or RDP ? Where's the issue?[Config] Configuring cisco router 837Cisco 867VAE-K9 - slow speed issuesAnyone still up to speed on ISDN (Cisco 804)? Forums → Equipment Support → Hardware By Brand → Cisco → [CCNA] CCNA 3550 switch with a warning error: switch core BIST uniqs5926 Share « [HELP] PPTP endpoint + Win 2003 IAS RADIUS = no required encrypt • Pix 501 timing out with SFTP connections » garysdenjoin:2005-12-27Washington, PA garysden Member 2007-Jan-5 5:13 pm [CCNA] CCNA 3550 switch with a warning error: switch core BISTI have switch that was given to me from work. It has issues and when I reconfigured it (I could not get into hyperterminal) it is on however I get this warning:!!! WARNING: The switch is not usable !!!Reason:Error with Switch Core BIST test.Returns: Test Complete Low : 0x00000011, Test Complete High : 0x000000FFAny help would be wonderful. · actions · 2007-Jan-5 5:13 pm · CovenantMVMjoin:2003-07-01England Covenant MVM 2007-Jan-5 5:44 pm Re: [CCNA] CCNA 3550 switch with a warning error: switch core BIBIST stands for Built in Self Test which is part of POST or Power On Self Test. (Gee, loads of acronyms and this is just the first sentence! )Normally you would see more output than this but that is neither here nor there. A problem with POST or BIST is usually due to a hardware failure which can't be recovered unfortunately by the end users and requires a RMA.If you know an electrical engineer, then you can ask them to have a look at it but in terms of its usefulness and recovery, it is an expensive door stop.Caveat: It has been postulated in various TAC docs and end
this morning.... anyone knows if my switch is dead ?... thanks ==================================================================== Cisco Internetwork Operating System Software IOS (tm) C3500XL Software (C3500XL-C3H2S-M), Version 12.0(5.4)WC(1), MAINTENANCE INTERIM SOFTWARE Copyright (c) 1986-2001 by cisco Systems, Inc. Compiled Tue 10-Jul-01 12:32 by devgoyal Image text-base: 0x00003000, data-base: 0x00333CD8 Initializing C3500XL flash... flashfs[1]: 164 files, 2 directories flashfs[1]: 0 orphaned files, 0 orphaned directories flashfs[1]: Total bytes: 3612672 flashfs[1]: Bytes used: 3132928 flashfs[1]: Bytes available: 479744 flashfs[1]: flashfs fsck took 5 seconds. http://www.dslreports.com/forum/r17585365-CCNA-CCNA-3550-switch-with-a-warning-error-switch-core-BIST flashfs[1]: Initialization complete. ....done Initializing C3500XL flash. C3500XL POST: System Board Test: Passed C3500XL POST: Daughter Card Test: Passed C3500XL POST: CPU Buffer Test: Passed C3500XL POST: CPU Notify RAM Test: Passed C3500XL POST: CPU Interface Test: Passed C3500XL POST: Testing Switch Core: Passed Error with Switch Core BIST test Phase 0. Returns: Test Complete Low : 0x077773FF, Test Complete High http://www.velocityreviews.com/threads/my-cisco-catalyst-3500-xl-switch-is-dead.535156/ : 0x37777372 Test Phase Low : 0x00000008, Test Phase High : 0x00000000 Test Phase Third : 0x00000000, Test Complete Third : 0x00000060 C3500XL POST FAILURE: Testing Switch Core: Failed C3500XL POST FAILURE: Testing Buffer Table: Failed C3500XL POST FAILURE: Data Buffer Test: Failed C3500XL POST FAILURE: Configuring Switch Parameters: Failed C3500XL POST FAILURE: Switch Core BIST faile C3500XL POST FAILURE: Cannot test Modules due to failure of Switch Core POST Del Mar Failure (0th Del Mar): req system failed to init C3500XL POST FAILURE: C3500XL POST FAILURE: ATM: required system failed to init C3500XL POST: Ethernet Controller Test: Passed C3500XL POST FAILURE: MII Test: Failed C3500XL POST FAILURE: Error waiting for Ethernet Controller and SW_PARAMS C3500XL POST FAILURE: Initialization/POST failed C3500XL POST FAILURE: AT: Failing because system POST failed Exception (8192)! Debug Exception (Could be NULL pointer dereference) CPU Register Context: Vector = 0x00002000 PC = 0x000EEDE8 MSR = 0x00029200 CR = 0x22000024 LR = 0x000F203C CTR = 0x001D6D14 XER = 0x20000000 R0 = 0x00000000 R1 = 0x004B5558 R2 = 0x00000000 R3 = 0x00000000 R4 = 0x00000001 R5 = 0x000
RMA before? I am in a tough spot. I have a Cisco WS-C3550-48-SMI that has been at a http://www.genmay.com/showthread.php?t=780675 clients since they moved into the building a few years ago. Its fried. CPU is toast and it locks up during startup.Now my research shows that this switch http://www.ti.com/product/TMS570LS0432/datasheet among with several others, have a limited life time warranty (or 5 years after end of life). This is great and all, but NO one knows who installed error with or purchased the switch. I am afraid Cisco is going to say tough luck and my client will need a new $600 switch... Or am I just thinking to much about this? The reason I ask is because on their site, the RMA form asks for who you bought it from, their phone number, maintainance contract number, error with switch and serial number. I only have the serial number. Quote: Loading "flash:c3550-i9q3l2-mz.121-13.EA1a/c3550-i9q3l2-mz.121-13.EA1a.bin"...############################################# ############################################################ ############################################################ ############################################################ ############################################################ ############################################################ ######################################### File "flash:c3550-i9q3l2-mz.121-13.EA1a/c3550-i9q3l2-mz.121-13.EA1a.bin" uncompressed and installed, entry point: 0x3000 executing... Restricted Rights Legend Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c) of the Commercial Computer Software - Restricted Rights clause at FAR sec. 52.227-19 and subparagraph (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS sec. 252.227-7013. cisco Systems, Inc. 170 West Tasman Drive San Jose, California 95134-1706 Cisco Internetwork Operating System Software IOS (tm) C3550 Software (C3550-I9Q3L2-M), Version 12.1(13)EA1a, RELEASE SOFTWARE (fc1) Copyright (c) 1986-2003 by cisco Systems, Inc. Compiled Tue 25-Mar-03 23:21 by yenanh Image text-base: 0x00003000, data-base: 0x00654C9C Initializing flashfs... flashfs[1]: 18 files, 4 directories flashfs[1]: 0 orphaned files, 0 orphaned directories flashfs[1]: Total bytes: 15998976 flashfs[1]: Bytes used: 5258752 flashfs[1]: Bytes available: 10740224 flashfs[1]: flashfs fsck took 8 seconds. flashfs[1]: Initialization complete. ...done Initializing flashfs. POST: CPU Buffer Tests : Be
Silicon Errata (Silicon Revision B) (Rev. A) TMS570LS0x32 Microcontroller Silicon Errata (Silicon Rev A) (Rev. F) TMS570LS0x32 Microcontroller Silicon Errata (Silicon Revision 0) (Rev. B) TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (Rev. B) View more In English 中文内容 日本語表示 Description & parametrics Online datasheet Technical documents Tools & software Sample & buy Compare Quality & packaging Support & training Expand All 1 Device Overview 1.1 Features 1.2 Applications 1.3 Description 1.4 Functional Block Diagram 2 Revision History 3 Device Comparison 4 Terminal Configuration and Functions 4.1 PZ QFP Package Pinout (100-Pin) 4.2 Terminal Functions 4.2.1 High-End Timer (N2HET) 4.2.2 Enhanced Quadrature Encoder Pulse Modules (eQEP) 4.2.3 General-Purpose Input/Output (GPIO) 4.2.4 Controller Area Network Interface Modules (DCAN1, DCAN2) 4.2.5 Multibuffered Serial Peripheral Interface (MibSPI1) 4.2.6 Standard Serial Peripheral Interface (SPI2) 4.2.7 Local Interconnect Network Controller (LIN) 4.2.8 Multibuffered Analog-to-Digital Converter (MibADC) 4.2.9 System Module 4.2.10 Error Signaling Module (ESM) 4.2.11 Main Oscillator 4.2.12 Test/Debug Interface 4.2.13 Flash 4.2.14 Core Supply 4.2.15 I/O Supply 4.2.16 Core and I/O Supply Ground Reference 4.3 Output Multiplexing and Control 4.3.1 Notes on Output Multiplexing 4.3.2 General Rules for Multiplexing Control Registers 4.4 Special Multiplexed Options 4.4.1 Filtering for eQEP Inputs 4.4.1.1 eQEPA Input 4.4.1.2 eQEPB Input 4.4.1.3 eQEPI Input 4.4.1.4 eQEPS Input 4.4.2 N2HET PIN_nDISABLE Input Port 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Power-On Hours (POH) 5.4 Recommended Operating Conditions 5.5 Switching Characteristics Over Recommended Operating Conditions for Clock Domains 5.6 Wait States Required 5.7 Power Consumption 5.8 Thermal Resistance Characteristics for PZ 5.9 Input/Output Electrical Characteristics 5.10 Output Buffer Drive Strengths 5.11 Input Timings 5.12 Output Timings 6 System Information and Electrical Specifications 6.1 Voltage Monitor Characteristics 6.1.1 Important Considerations 6.1.2 Voltage Monitor Operation 6.1.3 Supply Filtering 6.2 Power Sequencing and Power-On Reset 6.2.1 Power-Up Sequence 6.2.2 Power-Down Sequence 6.2.3 Power-On Reset: nPORRST 6.2.3.1 nPORRST Electrical and Timing Requirements 6.3 Warm Reset (nRST) 6.3.1 Causes of Warm Reset 6.3.2 nRST Timing Requirements 6.4 ARM Cortex-R4 CPU Information 6.4.1 Summary of ARM Cortex-R4 CPU Features 6.4.2 ARM Cortex-R4 CPU Features Enabled by Software 6.4.3 Dual Core Imple