Parity Error Detected As Master On Secondary Bus
7200 Series RoutersTroubleshoot and AlertsTroubleshooting TechNotes Cisco 7200 Parity Error Fault Tree Download Print Available Languages Download Options PDF (49.3 KB) View with Adobe Reader on a variety of devices Updated:Apr 13, 2009 Document ID:12763 Contents Introduction Prerequisites Requirements Components Used Conventions Network Processing Engine (NPE) Parity Error Fault Tree Analysis NPE Parity Error Detection and Messages Parity Errors in the NPE-300 NPE-400 Parity/ECC Detection Parity Errors in the C7200 Router Solutions Related Information Introduction This document explains the steps to troubleshoot and isolate which part or component of a Cisco 7200 is failing when you identify a variety of parity error messages. We recommend that you read Troubleshooting Router Crashes and Processor Memory Parity Errors (PMPEs) before you proceed with this document. Note:The information in this document is based on the Cisco 7200 Series Routers. Prerequisites Requirements There are no specific prerequisites for this document. Components Used This document is not restricted to specific software and hardware versions. The information presented in this document was created from devices in a specific lab environment. All of the devices used in this document started with a cleared (default) configuration. If you work in a live network, ensure that you understand the potential impact of any command before you use it. Conventions For more information on document conventions, refer to the Cisco Technical Tips Conventions. Network Processing Engine (NPE) Parity Error Fault Tree Analysis This diagram describes the steps to determine which part or component of a Cisco 7200 is failing when you identify a variety of parity error messages. Note:Capture and record the show tech-support output and console logs, and collect all crashinfo files during parity error events. NPE Parity Error Detection and Messages This section contains block diagrams of the NPE and where these systems detect parity errors. You can find a description of each type of error message below. Parity Errors in the NPE-300 The N
integrity following parity error detection are described. In one embodiment, the method includes the blockage of bus transactions in response to detection of a parity error. Once bus transactions are suspended, a parity error handler routine...https://www.google.ch/patents/US20050193288?utm_source=gb-gplus-sharePatent US20050193288 - Apparatus and method for maintaining data integrity following parity error detection Erweiterte PatentsucheTry the new Google Patents, with machine-classified http://www.cisco.com/c/en/us/support/docs/routers/7200-series-routers/12763-c7200-faulttree.html Google Scholar results, and Japanese and South Korean patents. VeröffentlichungsnummerUS20050193288 A1PublikationstypAnmeldung AnmeldenummerUS 10/779,140 Veröffentlichungsdatum1. Sept. 2005Eingetragen13. Febr. 2004 Prioritätsdatum13. Febr. 2004Auch veröffentlicht unterCN1942863A, CN100501685C, EP1714214A1, US7251755, WO2005083568A1 Veröffentlichungsnummer10779140, 779140, US 2005/0193288 A1, US 2005/193288 A1, US https://www.google.ch/patents/US20050193288 20050193288 A1, US 20050193288A1, US 2005193288 A1, US 2005193288A1, US-A1-20050193288, US-A1-2005193288, US2005/0193288A1, US2005/193288A1, US20050193288 A1, US20050193288A1, US2005193288 A1, US2005193288A1 ErfinderAniruddha Joshi, John Lee, Geetani EdirisooriyaUrsprünglich BevollmächtigterJoshi Aniruddha P., Lee John P., Edirisooriya Geetani R.Zitat exportierenBiBTeX, EndNote, RefManPatentzitate (16), Referenziert von (2), Klassifizierungen (12), Juristische Ereignisse (3) Externe Links:USPTO, USPTO-Zuordnung, EspacenetApparatus and method for maintaining data integrity following parity error detection US 20050193288 A1 Zusammenfassung In some embodiments, a method and apparatus for maintaining data integrity following parity error detection are described. In one embodiment, the method includes the blockage of bus transactions in response to detection of a parity error. Once bus transactions are suspended, a pari
εμάς.Μάθετε περισσότερα Το κατάλαβαΟ λογαριασμός μουΑναζήτησηΧάρτεςYouTubePlayΕιδήσειςGmailDriveΗμερολόγιοGoogle+ΜετάφρασηΦωτογραφίεςΠερισσότεραΈγγραφαBloggerΕπαφέςHangoutsΑκόμη περισσότερα από την GoogleΕίσοδοςΚρυφά πεδίαΒιβλίαbooks.google.grhttps://books.google.gr/books/about/PCI_and_PCI_X_Hardware_and_Software.html?hl=el&id=pr4fspaQqZkC&utm_source=gb-gplus-sharePCI and PCI-X Hardware and SoftwareΗ βιβλιοθήκη μουΒοήθειαΣύνθετη Αναζήτηση ΒιβλίωνΑποκτήστε το εκτυπωμένο βιβλίοΔεν υπάρχουν διαθέσιμα eBookwww.digitalguru.comΕλευθερουδάκηςΠαπασωτηρίουΕύρεση σε κάποια βιβλιοθήκηΌλοι οι πωλητές»Αγορά βιβλίων στο Google PlayΠεριηγηθείτε στο μεγαλύτερο ηλεκτρονικό βιβλιοπωλείο του κόσμου και ξεκινήστε να διαβάζετε σήμερα στον ιστό, το tablet, το τηλέφωνο ή το ereader σας.Άμεση μετάβαση στο Google Play »PCI and PCI-X Hardware and Software: Architecture and DesignEdward Solari, George Willsewww.digitalguru.com, 2005 - 924 σελίδες 1 Κριτικήhttps://books.google.gr/books/about/PCI_and_PCI_X_Hardware_and_Software.html?hl=el&id=pr4fspaQqZkC Προεπισκόπηση αυτού του βιβλίου » Τι λένε οι χρήστες-Σύνταξη κριτικήςΔεν εντοπίσαμε κριτικές στις συνήθεις τοποθεσίες.Επιλεγμένες σελίδεςΣελίδα ΤίτλουΠίνακας περιεχομένωνΕυρετήριοΠεριεχόμεναISA System Architectural Overview 1 PCI and PCIX System Architectural Overview 7 Generic PCI Hardware Operation 37 and CDROM 4 Functional Interaction between PCI and PCIX Resources 63 and CDROM 5 Signal Line Definitio... Parity and Bus Errors 447 and CDROM 11 Reset Power and Signal Line Initialization 479 Signal Line Timing and Electrical Requirements CDROM 13 Connector Platform and AddIn Card Design CDROM 14 Latency and Performance 499 Mechanical Specification CDROM 16 System Resources 513 PCI Configuration Address Space 543 PCI Header Type 00H 569 and CDROM 19