Crc Error Bit Not 0
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CRC Error Bit is NOT 0. - on clocks. Started by jleslie48 ●April 9, 2009 ChronologicalNewest First Ok here's the story. I developed a message stream using a 32Mhz clock fpga putting out https://www.fpgarelated.com/showthread/comp.arch.fpga/84170-1.php 64 bits asynchronously using a dividing the clock by 8*2_000_000 (where 2_000_000 is http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2009-04/msg00290.html the baud rate, I know that's very fast for a baud rate) to get the sample rate for the bits. this resulted in a 2.00000 perfect divisor for the sampling rate for the comm line. I switched to a 40Mhz clock fpga, and with keeping the 8 and 2_000_000 numbers constant, crc error my previous perfect divisor for the sampling rate now shifts to 40M/(8*2M) == 2.5, and a bad drift occurs. So I think no problem lets just use 10 samples per bit rather than 8 thus changing the formula to 40M/(10*2M) == 2.000 and all will be fine again. And low and behold, Testbench confirms all is well. Now heres the problem, when I try and crc error bit load this program onto the Spartan 3 chip, it dies. with the above warning and the chip needs a power reset. Leaving the value of 10 in the sampling rate I can change the program from working to non working by playing with the following: -- Listing 7.3 -- JL 090309 changing hard coded '15' to (sb_tick-1) for length of -- each bit. hard coded '7' for databits now (dbit-1) as well. -- JL 090312 custom version of uart_tx for the 2mhz comm link. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity uart40_tx is generic( DBIT: integer:=64; -- # data bits SB_TICK: integer:=10 -- # ticks for each bit ); port( clk, reset : in std_logic; tx_start : in std_logic; s_tick : in std_logic; din : in std_logic_vector((dbit-1) downto 0); tx_done_tick : out std_logic; tx : out std_logic ); end uart40_tx ; architecture arch of uart40_tx is type state_type is (idle, start, data, stop); constant go_high : std_logic := '1'; constant go_low : std_logic := '0'; signal state_reg, state_next: state_type; signal s_reg, s_next: unsigned(7 downto 0); signal n_reg, n_next: unsigned(7 downto 0); signal b_reg, b_next: std_logic_vector((dbit-1) downto 0); signal tx_reg, tx_next: std_logic; signal bit_length
clock fpga ... I switched to a 40Mhz clock fpga, I still have no idea why making the loop iterate 10 times vs 9 would result in such catastrophic failure. Maybe the failure is due to increasing the clock frequency. What does static timing say about Fmax? -- Mike Treseler . Follow-Ups: Re: warning:impact:2217 error shows in the status register, CRC Error Bit is NOT 0. - on clocks. From: jleslie48 References: warning:impact:2217 error shows in the status register, CRC Error Bit is NOT 0. - on clocks. From: jleslie48 Re: warning:impact:2217 error shows in the status register, CRC Error Bit is NOT 0. - on clocks. From: Antti.Lukats@xxxxxxxxxxxxxx Re: warning:impact:2217 error shows in the status register, CRC Error Bit is NOT 0. - on clocks. From: jleslie48 Prev by Date: Microblaze GPIO API functions Next by Date: Re: buy XSA-50 Previous by thread: Re: warning:impact:2217 error shows in the status register, CRC Error Bit is NOT 0. - on clocks. Next by thread: Re: warning:impact:2217 error shows in the status register, CRC Error Bit is NOT 0. - on clocks. Index(es): Date Thread Flag as inappropriate (AWS) Security UNIX Linux Coding Usenet ArchiveAboutPrivacyImprint newsgroups.derkeiler.com >Archive >Comp >comp.arch.fpga >2009-04