Range Must Be Bounded By Constant Expressions Verilog Error
Contents |
here for a quick overview of the site Help Center Detailed answers to any questions you might have Meta Discuss the workings and policies of this site About Us verilog variable part select Learn more about Stack Overflow the company Business Learn more about hiring developers
Range Width Must Be Constant Expression
or posting ads with us Stack Overflow Questions Jobs Documentation Tags Users Badges Ask Question x Dismiss Join the Stack verilog range Overflow Community Stack Overflow is a community of 6.2 million programmers, just like you, helping each other. Join them; it only takes a minute: Sign up Verilog range must be bounded by constant
Verilog Index
expression up vote 0 down vote favorite I'm having trouble figuring out how to translate this VHDL code to Verilog. v_Upper := r_Digit_Index*4 + 3; v_Lower := r_Digit_Index*4; v_BCD_Digit := unsigned(r_BCD(v_Upper downto v_Lower)); if v_BCD_Digit > 4 then v_BCD_Digit := v_BCD_Digit + 3; end if; r_BCD(v_Upper downto v_Lower) <= std_logic_vector(v_BCD_Digit); If I try doing this in Verilog, I get the error, "Range Must be Bound by Constant systemverilog localparam Expression." I understand the error, but I can't figure out a good way to get around this. Essentially I want to parse a specific nibble of r_BCD, update it if it needs updating, then write it back into the same location that I pulled it from. Would a 2D array be better here? Here's the line of Verilog code causing the problem:+ r_BCD[r_Digit_Index*4 + 3:r_Digit_Index*4] <= w_BCD_Digit + 3; vhdl verilog share|improve this question edited Aug 4 '14 at 17:52 asked Aug 4 '14 at 17:05 Russell 2,1861023 Why didn't you post your verilog code here? –Qiu Aug 4 '14 at 17:41 @Qui see updated question. –Russell Aug 4 '14 at 17:52 add a comment| 1 Answer 1 active oldest votes up vote 1 down vote accepted In verilog you can not have a variable selection like that. ie r_BCD[r_Digit_Index*4 + 3:r_Digit_Index*4] is not allowed. Since 2001 you can do variable part-select using the special +: syntax. for example : r_BCD[r_Digit_Index*4 +: 4] //[ index +: width] For more info see Sutherland 2001 part 1-48. share|improve this answer answered Aug 4 '14 at 18:54 Morgan 12.9k43054 That powerpoint was very helpful, thank you
here for a quick overview of the site Help Center Detailed answers to any questions you might have Meta Discuss the workings and policies of this site About Us Learn more about Stack Overflow the company Business Learn more about hiring developers or posting ads with us Stack Overflow Questions Jobs Documentation Tags Users Badges Ask Question x Dismiss Join the Stack Overflow Community Stack Overflow is a community of 6.2 million programmers, just like you, helping each other. Join them; it only takes a minute: Sign up regarding error “Range must be bounded by constant expressions” up vote 1 down vote favorite 2 always @(numint or numfrac) begin begin : BIT_DET for (i=22;i>0;i=i-1) begin if http://stackoverflow.com/questions/25123924/verilog-range-must-be-bounded-by-constant-expression (numint[i]==1'b1) begin ieeesign <= numsign ; ieeeexp [7:0] <= 127+i; ieeemant[22:0] <= { numint[i-1:0] , numfrac[22:i] } ; ieeeop [31:0] <= { ieeesign, ieeeexp , ieeemant[22:0] } ; disable BIT_DET; end end end end endmodule Please tell me how can i remove the error? verilog share|improve this question edited Jan 5 '13 at 13:37 Rhymoid 6,62622253 asked Jan 5 '13 at 12:33 S Venu Madhav Chitta 4219 1 Is that the full text of the error? What http://stackoverflow.com/questions/14171833/regarding-error-range-must-be-bounded-by-constant-expressions line is it on? Your question could use a little more information. –Tim Jan 6 '13 at 4:38 add a comment| 1 Answer 1 active oldest votes up vote 4 down vote accepted The error is for [i-1:0] and [22:i]. Part-select cannot have a variable range. Bit-select can use a variable. Each bit of ieeemant needs to be assigned individually. Change: ieeemant[22:0] <= { numint[i-1:0] , numfrac[22:i] } ; to: for(j=0; j<23; j+=1) begin ieeemant[j] <= (i+j < 23) ? numfrac[j+i] : numint[j-i]; end share|improve this answer answered Jan 9 '13 at 18:39 Greg 10k51939 add a comment| Your Answer draft saved draft discarded Sign up or log in Sign up using Google Sign up using Facebook Sign up using Email and Password Post as a guest Name Email Post as a guest Name Email discard By posting your answer, you agree to the privacy policy and terms of service. Not the answer you're looking for? Browse other questions tagged verilog or ask your own question. asked 3 years ago viewed 2548 times active 3 years ago Blog Stack Overflow Podcast #92 - The Guerilla Guide to Interviewing Related 3Unknown verilog error 'expecting “endmodule”'3“
Help Rules Groups Blogs What's New? Teardown Videos Datasheets Advanced Search Forum Digital Design and Embedded Programming ASIC Design Methodologies and Tools (Digital) range must be bounded by constant expression in verilog? + Post New http://www.edaboard.com/thread124700.html Thread Results 1 to 2 of 2 range must be bounded by constant expression in https://groups.google.com/d/topic/comp.lang.verilog/v2AK6le-Rcw verilog? LinkBack LinkBack URL About LinkBacks Thread Tools Show Printable Version Download This Thread Subscribe to this Thread… Search Thread Advanced Search 30th April 2008,23:52 #1 gvm0072002 Newbie level 2 Join Date Jan 2007 Posts 2 Helped 0 / 0 Points 1,062 Level 7 range must be bounded by constant expressions for(i=0;i<56;i=i+8) begin if (string[i+7:i]<="G") y[i+7:i]<="C"; must be ijust want to know what is wrong in the above statement, it is showing an error of range must be bounded by constant expression(verilog). 30th April 2008,23:52 1st May 2008,09:41 #2 nand_gates Advanced Member level 3 Join Date Jul 2004 Posts 892 Helped 172 / 172 Points 9,086 Level 22 verilog range Here you must have declared string as reg [56*8:1] string; And verilog standard says that you can range must be not assign variable part select of a vector; that means string[i+7:i] is not allowed if i is not a constant. parameter i = 10; string [i+7:i] = 'A'; is allowed and valid. In ur case what you can do is declare string as array of chracters Code: reg [8:1] y_array [0:55]; reg [8:1] string_array [0:55]; //56 character array wire [56*8:1] string, y; for (i=0; i<56; i=i+1) begin if (string_array[i] <= 'G') y_array[i] <= 'C'; end assign string = {string_array[55], ........, string_array[0]}; assign y = {y_array[55], ......., y_array[0]}; Hope this helps! Hope this helps! + Post New Thread Please login « What happens if you supply more current | flicker noise in VHDL-AMS » Similar Threads SPI-4.2 (preconfigured bounded interval) (0) Non-constant part select error in Verilog! (2) Constant Voltage/Constant Current Circuit? (7) verilog Z value in expression (4) Problem with a constant parameter in Verilog code (0) Part and Inventory Search Top Helped / Month FvM (64), KlausST (50), ads-ee (36), Warpspeed (20), betwixt (20) Welcome to EDABoard.com EE World Online Sponsor New Posts calculate duty cycle using pic mikrocontroller (10) how to use Timer to generate many sequence (4) No output from Pulse Tranformer (8) Solar Panel reverse polarity protection (0) Event Driven Timer with rotary switch selection (3) Aut
inHidden fieldsSearch for groups or messages