Error Vcom-1136 Unknown Identifier
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hiring developers or posting ads with us Stack Overflow Questions Jobs Documentation Tags Users Badges Ask Question x Dismiss Join library unisim not found the Stack Overflow Community Stack Overflow is a community of 4.7 million programmers, just like you, helping each other. Join them; it only takes a minute: Sign up ModelSIM ALTERA error up unisim library download vote 0 down vote favorite I have the following code, to test in Altera ModelSim one memory ROM. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std_unsigned.all; ENTITY hex_vhdl_vhd_vec_tst IS END hex_vhdl_vhd_vec_tst; ARCHITECTURE hex_vhdl_arch OF hex_vhdl_vhd_vec_tst IS -- constants -- signals SIGNAL t_sig_address : STD_LOGIC_VECTOR(10 DOWNTO 0); SIGNAL t_sig_clock : STD_LOGIC; SIGNAL t_sig_q : STD_LOGIC_VECTOR(7 DOWNTO 0); COMPONENT hex_vhdl PORT( address : IN STD_LOGIC_VECTOR(10 DOWNTO 0); clock :
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IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; BEGIN tb : hex_vhdl PORT MAP( -- list connections between master ports and signals address => t_sig_address, clock => t_sig_clock, q => t_sig_q ); TEST: PROCESS variable L : natural; begin --clock for L in 0 to 2048 loop t_sig_clock <= '0'; WAIT FOR 25 ns; t_sig_clock <= '1'; WAIT FOR 25 ns; t_sig_address <= std_logic_vector(to_unsigned(L, 11)); end loop; t_sig_clock <= '0'; wait; END PROCESS TEST; END hex_vhdl_arch; The code in the PROCESS part, was designed by me. I'm tempted not use more the address change step by step... Before, I had to make a PROCESS for each bit address. The only line that does not compile is t_sig_address <= std_logic_vector(to_unsigned(L, 11)); # ** Error: hex_vhdl.vht(70): (vcom-1136) Unknown identifier "to_unsigned". So I added the following line at the beginning USE ieee.numeric_std_unsigned.all; But, started a following error # ** Error: (vcom-11) Could not find ieee.numeric_std_unsigned. # ** Error: hex_vhdl.vht(30): (vcom-1195) Cannot find expanded name "ieee.numeric_std_unsigned". # ** Error: hex_vhdl.vht(30): Unknown expanded name. I made these arrangements with the clues, that I found in the links bellow Illegal type conversion VHDL Convert Integer to s
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10 of 21 Thread: inout Std_logic_vector Signal Test Thread Tools Show Printable Version Email this Page… Subscribe to this Thread… Search Thread Advanced Search Display Linear Mode Switch to Hybrid Mode Switch to Threaded Mode November http://stackoverflow.com/questions/28031531/modelsim-altera-error 2nd, 2011,02:55 AM #1 alterahenry View Profile View Forum Posts Altera Teacher Join Date Oct 2010 Posts 76 Rep Power 1 inout Std_logic_vector Signal Test Hi, I am getting the following error by writting a testbench for Asynchrone SRAM and I have tried to solve this unsucessfully.Please any advice Error Output: # ** Error: Z:/Prototyp/Development_Infos_Collection/LS4000_Development/HW/FPGA/Tutorial/Simulation/Projects/sram1024kx8/tsram1024kx8.vhd(12): (vcom-1136) Unknown identifier "std_logic_vector". VHDL Code: Code: entity test_sram1024x8 is Line 12 PORT ( D : inout Std_logic_vector(7 downto 0)); http://www.alteraforum.com/forum/showthread.php?t=32528 end; architecture test of test_sram1024x8 is COMPONENT sram1024x8 port (A : in Std_logic_vector(19 downto 0); D : inout Std_logic_vector(7 downto 0); nCE : in std_logic; nCE2 : in std_logic; nWE : in std_logic; nOE : in Std_logic); END COMPONENT ; SIGNAL A : bit := '0'; SIGNAL nCE : bit := '1'; SIGNAL nCE2 : bit := '1'; SIGNAL nWE : bit := '1'; SIGNAL nOE : bit := '0'; begin dut : sram1024x8 PORT MAP ( A => A, D => D, nCE => nCE, nCE2 => nCE2, nWE => nWE, nOE => nOE ); --clock : PROCESS --begin --wait for 10 ns; clk <= not clk; --end PROCESS clock; stimulus : PROCESS begin --A <= '1'; wait for 5 ns; nCE <= '0'; wait for 5 ns; nCE2 <= '0'; wait for 5 ns; nOE <= '1'; wait for 12 ns; nWE <= '0'; wait; end PROCESS stimulus; end test; Reply With Quote November 2nd, 2011,03:15 AM #2 Tricky View Profile View Forum Posts Moderator **Forum Master** Join Date Oct 2008 Posts 5,088 Rep Power 1 Re: inout Std_logic_vector Signal Test you have probably forgotten to include thse lines: library ieee; use ieee.std_logic_1164.all; Reply With Quote November 2nd, 2011,03:16 AM #3 Tricky View Profile View Forum Posts Moderator **Forum Master** Join Date Oct 2008 Posts 5,088 Rep Power 1 Re: inout St
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