Error Resilient Motion Estimation Architecture
Communication, Networking & Broadcasting Components, Circuits, Devices & Systems Computing & Processing Engineered Materials, Dielectrics & Plasmas Engineering Profession Fields, Waves & Electromagnetics General Topics for Engineers Geoscience Nuclear Engineering Photonics & Electro-Optics Power, Energy, & Industry Applications Robotics & Control Systems Signal Processing & Analysis Transportation Browse Books & eBooks Conference Publications Courses Journals & Magazines Standards By Topic My Settings Content Alerts My Projects Search Alerts Preferences Purchase History Search History What can I access? Get Help About IEEE Xplore Feedback Technical Support Resources and Help Terms of Use What Can I Access? Subscribe Personal Sign In Create Account IEEE Account Change Username/Password Update Address Purchase Details Payment Options Order History View Purchased Documents Profile Information Communications Preferences Profession and Education Technical Interests Need Help? US & Canada: +1 800 678 4333 Worldwide: +1 732 981 0060 Contact & Support About IEEE Xplore Contact Us Help Terms of Use Nondiscrimination Policy Sitemap Privacy & Opting Out of Cookies A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.© Copyright 2016 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
Submission Guidelines Research Article Open Access Error Resilience in Current Distributed Video Coding ArchitecturesClaudiaTonoli1, PierangeloMigliorati1Email author and RiccardoLeonardi1EURASIP Journal on Image and Video Processing20092009:946585DOI: 10.1155/2009/946585© Claudia Tonoli et al.2009Received: 19May2008Accepted: 15January2009Published: 1April2009 AbstractIn distributed video coding the signal prediction is shifted at the decoder side, giving therefore most of the computational complexity burden at the receiver. Moreover, since no prediction loop exists before transmission, an intrinsic robustness to transmission errors has been claimed. This work evaluates and compares the error resilience performance of two distributed video coding architectures. In particular, we have considered a video codec based on the http://ieeexplore.ieee.org/abstract/document/4629348/ Stanford architecture (DISCOVER codec) and a video codec based on the PRISM architecture. Specifically, an accurate temporal and rate/distortion based evaluation of the effects of the transmission errors for both the considered DVC architectures has been performed and discussed. These approaches have been also compared with H.264/AVC, in both cases of no error protection, and simple FEC error protection. Our evaluations have highlighted in all cases a http://jivp.eurasipjournals.springeropen.com/articles/10.1155/2009/946585 strong dependence of the behavior of the various codecs to the content of the considered video sequence. In particular, PRISM seems to be particularly well suited for low-motion sequences, whereas DISCOVER provides better performance in the other cases. 1. IntroductionDistributed video coding (DVC) is attracting some attention due to the potential innovative application perspectives with respect to the more traditional approaches (see, e.g., [1]). DVC is based on the principles of distributed source coding (DSC), a branch of information theory introduced in the 70s by Slepian and Wolf [2] and Wyner and Ziv [3], which have been applied to the transmission of a video sequence. The main idea of DVC attempts to exploit the temporal correlation of a video signal in the decoding phase rather than in the encoding one. In this way, the classic motion compensated prediction is not performed any longer at the encoder, with a consequent significant reduction in the computational complexity of the encoder. DSC principles are used instead. The encoding rate is reduced by transmitting only the parity bits of a suitable systematic channel code, which are extracted from the original frames that need to be sent. At the decoder, the redundancy of the vide
von GoogleAnmeldenAusgeblendete FelderBooksbooks.google.de - Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power https://books.google.com/books?id=z-_iy5hAtfAC&pg=PA275&lpg=PA275&dq=error+resilient+motion+estimation+architecture&source=bl&ots=Q8744GhrYq&sig=44CoD5z8hiNFEzcc-EBAB7FfT9A&hl=en&sa=X&ved=0ahUKEwiI_7zi49LPAhVK8mMKHYj_BT design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations....https://books.google.de/books/about/Low_Power_Variation_Tolerant_Design_in_N.html?hl=de&id=z-_iy5hAtfAC&utm_source=gb-gplus-shareLow-Power Variation-Tolerant Design in Nanometer SiliconMeine BücherHilfeErweiterte BuchsucheE-Book kaufen - 91,62 €Nach Druckexemplar suchenSpringer ShopAmazon.deBuch.deBuchkatalog.deLibri.deWeltbild.deIn Bücherei suchenAlle Händler»Low-Power Variation-Tolerant Design in Nanometer SiliconSwarup Bhunia, error resilient Saibal MukhopadhyaySpringer Science & Business Media, 10.11.2010 - 440 Seiten 0 Rezensionenhttps://books.google.de/books/about/Low_Power_Variation_Tolerant_Design_in_N.html?hl=de&id=z-_iy5hAtfACDesign considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on error resilient motion parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes. Voransicht des Buches » Was andere dazu sagen-Rezension schreibenEs wurden keine Rezensionen gefunden.Ausgewählte SeitenSeite 13TitelseiteInhaltsverzeichnisIndexInhaltPart II CircuitLevel Design Solutions81 Part III SystemLevel Design Solutions208 Part IV LowPower and Robust Reconfigurable Computing334 Index435 Urheberrecht Andere Ausgaben - Alle anzeigenLow-Power Variation-Tolerant Design in Nanometer SiliconSwarup Bhunia,Saibal MukhopadhyayKeine Leseprobe verfügbar - 2014Low-Power Variation-Tolerant Design in Nanometer SiliconSwarup Bhunia,Saibal MukhopadhyayKeine Leseprobe verfügbar - 2011Low-Power Variation-Tolerant Design in Nanometer SiliconSwarup Bhunia,S
be down. Please try the request again. Your cache administrator is webmaster. Generated Thu, 13 Oct 2016 04:09:00 GMT by s_ac5 (squid/3.5.20)