Error Resilient System Architecture Ersa For Probabilistic Applications
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the article in the profile.DoneDuplicate citationsThe following articles are merged in Scholar. Their combined citations are counted only for the first article.DoneMerge duplicatesCitations per yearScholarFollowEmailFollow new articlesFollow new citationsCreate alertCancelHyungmin ChoIntel CoporationComputer Architecture, Hardware Reliability, Error ResilienceVerified email at intel.comScholarGet my own profileGoogle ScholarCitation indicesAllSince 2011Citations474432h-index77i10-index652009201020112012201320142015201614213437619812774Title1–15Cited byYearERSA: Error resilient system architecture for probabilistic applicationsL Leem, H Cho, J Bau, QA Jacobson, S Mitra2010 Design, Automation & Test in http://ieeexplore.ieee.org/iel5/5450668/5456897/05457059.pdf?arnumber=5457059 Europe Conference & Exhibition (DATE 2010 ..., 20101982010Quantitative evaluation of soft error injection techniques for robust system designH Cho, S Mirkhani, CY Cher, JA Abraham, S MitraDesign Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE, 1-10, 2013702013Ersa: Error resilient system architecture for probabilistic applicationsH Cho, L Leem, S MitraIEEE http://scholar.google.com/citations?user=wJDylfAAAAAJ&hl=en Transactions on Computer-Aided Design of Integrated Circuits and ..., 2012642012Gallager B decoder on noisy hardwareSMST Yazdi, H Cho, L DolecekIEEE Transactions on Communications 61 (5), 1660-1673, 2013522013Dynamic data scratchpad memory management for a memory subsystem with an MMUH Cho, B Egger, J Lee, H ShinACM SIGPLAN Notices 42 (7), 195-206, 2007512007Cross-layer error resilience for robust systemsL Leem, H Cho, HH Lee, YM Kim, Y Li, S MitraProceedings of the International Conference on Computer-Aided Design, 177-180, 2010102010The resilience wall: Cross-layer solution strategiesS Mitra, P Bose, E Cheng, CY Cher, H Cho, R Joshi, YM Kim, CR Lefurgy, ...Proceedings of Technical Program-2014 International Symposium on VLSI ..., 201492014Probabilistic analysis of Gallager B faulty decoderSMST Yazdi, H Cho, Y Sun, S Mitra, L Dolecek2012 IEEE International Conference on Communications (ICC), 7019-7023, 201272012Understanding soft errors in uncore componentsH Cho, CY Cher, T Shepherd, S Mitra2
von GoogleAnmeldenAusgeblendete FelderBooksbooks.google.de - Design considerations for low-power operations and robustness https://books.google.com/books?id=z-_iy5hAtfAC&pg=PA275&lpg=PA275&dq=error+resilient+system+architecture+ersa+for+probabilistic+applications&source=bl&ots=Q8744H8qWy&sig=hrvZ_4jptuZmTv0fMRBNTAwzXQU&hl=en&sa=X&ved=0ahUKE with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations....https://books.google.de/books/about/Low_Power_Variation_Tolerant_Design_in_N.html?hl=de&id=z-_iy5hAtfAC&utm_source=gb-gplus-shareLow-Power Variation-Tolerant Design in Nanometer error resilient SiliconMeine BücherHilfeErweiterte BuchsucheE-Book kaufen - 91,62 €Nach Druckexemplar suchenSpringer ShopAmazon.deBuch.deBuchkatalog.deLibri.deWeltbild.deIn Bücherei suchenAlle Händler»Low-Power Variation-Tolerant Design in Nanometer SiliconSwarup Bhunia, Saibal MukhopadhyaySpringer Science & Business Media, 10.11.2010 - 440 Seiten 0 Rezensionenhttps://books.google.de/books/about/Low_Power_Variation_Tolerant_Design_in_N.html?hl=de&id=z-_iy5hAtfACDesign considerations for low-power operations and error resilient system robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes. Voransicht des Buches » Was andere dazu sagen-Rezension schreibenEs wurden keine Rezensionen ge
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