Error Unable To Bind Wire/reg/memory
here for a quick overview of the site Help Center Detailed answers to any questions you might have Meta Discuss the workings and policies of this site About Us Learn more about Stack Overflow the company Business Learn more about hiring developers or posting ads with us Stack Overflow Questions Jobs Documentation Tags Users Badges Ask Question x Dismiss Join the Stack Overflow Community Stack Overflow is a community of 4.7 million programmers, just like you, helping each other. Join them; it only takes a minute: Sign up hdl verilog Compiler Errors up vote -1 down vote favorite When I first tried to compile my code, I only had syntax errors and was able to fix them. Now I have errors that I cannot figure out at all. I don't know how to fix. Here is my current code: module p_5 (output y_out, input x_in, clk, reset_b); parameter s_a = 2'd0; parameter s_b = 2'd1; parameter s_c = 2'd2; reg Set_flag; reg Clr_flag; reg [1:0] state, next_state; assign y_out = (state == s_b) || (state == s_c) ; always @ (posedge clk) if (reset_b == 1'b0) state <= s_a; else state <= next_state; always @ (state, x_in, flag) begin next_state = s_a; Set_flag = 0; Clr_flag = 0; case (state) s_a: if ((x_in == 1'b1) && (flag == 1'b0)) begin next_state = s_a; Set_flag = 1; end else if ((x_in == 1'b1) && (flag == 1'b1)) begin next_state = s_b; Set_flag = 0; end else if (x_in == 1'b0) next_state = s_a; s_b: if (x_in == 1'b0) next_state = s_b; else begin next_state = s_c; Clr_flag = 1; end s_c: if (x_in == 1'b0) next_state = s_c; else next_state = s_a; default: begin next_state = s_a; Clr_flag = 1'b0; Set_flag = 1'b0; end endcase end always @ (posedge clk) if (reset_b == 1'b0) flag <= 0; else if (Set_flag) flag <= 1'b1; else if (Clr_flag) flag <= 1'b0; endmodule This is the test bench: module test_5 (); wire y_out; reg x_in, clk, flag, reset_b; p_5 M0 (y_out, x_in, clk, reset_b); initial #500 $finish; initial begin clk = 0; forever #5 clk = !clk; end initial fork reset_b = 1'b0; #20 reset_b = 1; #20 x_in = 1'b0; #40 x_in = 1'b1; #50 x_in = 1'b0; #80 x_in = 1'b1; #100 x_in = 0; #150 x_in = 1'b1; #160 x_in = 1'b0; #200 x_in = 1'b1; #230 reset_b = 1'b0; #250 reset_b = 1'b1; #300 x_in = 1'b0; #300 flag = 1'b0; join endmodule Errors: p5.v:22: error: Unable to bind wire/reg/memory `flag' in `t_ques_5_50.M0' p5.v:22: error: Unable to elaborate condition expression. p5.v:17: error: Unable to bind wire/reg/memory `flag' in `t_ques_5_50.M0' flag p5.v:36: error: Could not find variable ``flag'' in ``t_ques_5_50.M0'' p5.v:37: error: Could not find variable ``flag'' in ``t_ques_5_50.M0'' p5.v:38: error: Could not find variable ``flag'' in ``t_ques_5_50.M0'' 7
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From: Guy Hutchison Join INTELLIGENT WORK FORUMSFOR COMPUTER PROFESSIONALS Log In Come Join Us! Are you aComputer / IT professional?Join Tek-Tips Forums! Talk With Other Members Be Notified Of ResponsesTo Your Posts Keyword http://www.tek-tips.com/viewthread.cfm?qid=1053251 Search One-Click Access To YourFavorite Forums Automated SignaturesOn Your Posts Best Of All, It's Free! Join Us! *Tek-Tips's functionality depends on members receiving e-mail. By joining you are opting in to receive http://archives.seul.org/geda/user/Aug-2004/msg00033.html e-mail. Posting Guidelines Promoting, selling, recruiting, coursework and thesis posting is forbidden.Tek-Tips Posting Policies Jobs Jobs from Indeed What: Where: jobs by Link To This Forum! Add Stickiness To Your Site By error unable Linking To This Professionally Managed Technical Forum.Just copy and paste the BBCode HTML Markdown MediaWiki reStructuredText code below into your site. Verilog Forum at Tek-Tips HomeForumsProgrammersLanguagesVerilog Forum beginner probl. code testing bind wire reg int & declaration thread283-1053251 Forum Search FAQs Links MVPs beginner probl. code testing bind wire reg int & declaration beginner probl. code testing bind wire reg int & declaration marc3 error unable to (Programmer) (OP) 2 May 05 11:15 I have some difficultis with the test of the following code.Can some one tell me why it doesn't work?Hier is the message from iverilog about the faultC:\iverilog\ubung> ..\bin\iverilog.exe jkff.vljkff.vl:34: error: q is not a reg/integer/time in test.jkff.vl:28:: q is declared here as wire.Of course it is only an abstractHier is the code I am testing module jkff(q, j, k, clk);input j, k, clk;output q;reg q;always @(posedge clk)if((j==1) && (q==0))q <= j;else if((k==1) && (q==1))q <= 0;else if((k==0) && (q==1))q <= q;elseq <= 0;initial begin $dumpfile("jkff.vcd");$dumpvars(0);endendmodulemodule test();reg j, k, clk;wire q;jkff testjkff(q, j, k, clk);initial beginclk = 0;#2 q = 0; j = 0; k = x;#4 q = 0; j = 1; k = x;#6 q = 1; j = x; k = 1;#8 q = 1; j = x; k = 0;#4 q = 0; j = 0; k = x;#8 q = 0; j = 1; k = x;#16 q = 1; j = x; k = 1;#32 q = 1; j = x; k = 0;#200 $finish;endalways @(clk) beginclk <= !clk;$display("Q+=%0b J=%0b K=%0b clk=%0b time=%0t", q, j, k, clk, $time);endendmodule RE: begin 11 Aug 2004 17:34:37 -0700 Delivered-to: archiver@seul.org Delivered-to: geda-user-outgoing@seul.org Delivered-to: geda-user@moria.seul.org Delivery-date: Wed, 11 Aug 2004 20:34:41 -0400 Reply-to: geda-user@seul.org Sender: owner-geda-user@seul.org User-agent: Mozilla Thunderbird 0.7.2 (Windows/20040707) This may have already been reported as a bug, but I'll send this in just in case. I'm trying to simulate a placed and routed xilinx design from which the xilinx tool has generated a gate level module. Iverilog is having trouble with the xilinx sim primitives that get instantiated.. iverilog -y /usr/local/xilinx/verilog/src/simprims zsimtest.v /usr/local/xilinx/verilog/src/simprims/X_TRI.v:17: warning: choosing typ expression. /usr/local/xilinx/verilog/src/simprims/X_TRI.v:17: warning: choosing typ expression. /usr/local/xilinx/verilog/src/simprims/X_TRI.v:18: warning: choosing typ expression. /usr/local/xilinx/verilog/src/simprims/X_TRI.v:18: warning: choosing typ expression. /usr/local/xilinx/verilog/src/simprims/X_TRI.v:19: warning: choosing typ expression. /usr/local/xilinx/verilog/src/simprims/X_TRI.v:19: warning: choosing typ expression. /usr/local/xilinx/verilog/src/simprims/X_TRI.v:20: warning: choosing typ expression. /usr/local/xilinx/verilog/src/simprims/X_TRI.v:20: warning: choosing typ expression. /usr/local/xilinx/verilog/src/simprims/X_INV.v:17: warning: choosing typ expression. /usr/local/xilinx/verilog/src/simprims/X_INV.v:17: warning: choosing typ expression. /usr/local/xilinx/verilog/src/simprims/X_FF.v:37: parse error /usr/local/xilinx/verilog/src/simprims/X_FF.v:31: error: syntax error in specify block zsimtest.v:14: error: Unable to bind wire/reg/memory `ztest' in `zsimtest' 1 error(s) during elaboration. ... It appears to me that there is a problem with the specify block? I've got icarus running on 3 different platforms: RH Linux, Cygwin and Mac OSX -same thing on all three. My goal is to simulate the gate level fpga module with back-annotated sdf info. I can send the .v files for the simprims in question if you don't already have them. I can send the gate level module and tbench if you think that would be necessary. Is it something I'm doing or is it a bug? Is there a work around? Laurin Blacken Follow-Ups: Re: gEDA-user: iverilog parse bug? From: John Sheahan