Page Fault Error Code Bits
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Stack-Segment Fault 1.1.8 General Protection Fault 1.1.9 Page Fault 1.1.9.1 Error code 1.1.10 x87 Floating-Point Exception 1.1.11 Alignment Check 1.1.12 SIMD Floating-Point Exception 1.2 Traps 1.2.1 Debug 1.2.2 Breakpoint 1.2.3 Overflow 1.3 Aborts 1.3.1 Double Fault 1.3.2 Machine exception 13 general protection fault Check 1.3.3 Triple Fault 2 Selector Error Code 2.1 Legacy 2.1.1 FPU Error Interrupt 2.1.2 general protection fault error code Coprocessor Segment Overrun 3 See Also 3.1 External Links Exceptions as described in this article are generated by the CPU when an
X86 Exceptions
'error' occurs. Some exceptions are not really errors in most cases, such as page faults. Exceptions are a type of interrupt. Exceptions are classified as: Faults: These can be corrected and the program may continue as
Invalid Opcode Exception X64 Exception Type 06
if nothing happened. Traps: Traps are reported immediately after the execution of the trapping instruction. Aborts: Some severe unrecoverable error. Some exceptions will push a 32-bit "error code" on to the top of the stack, which provides additional information about the error. This value must be pulled from the stack before returning control back to the currently running program. (i.e. before calling IRET) Name Vector nr. Type Mnemonic Error code? Divide-by-zero Error x86 exception handling 0 (0x0) Fault #DE No Debug 1 (0x1) Fault/Trap #DB No Non-maskable Interrupt 2 (0x2) Interrupt - No Breakpoint 3 (0x3) Trap #BP No Overflow 4 (0x4) Trap #OF No Bound Range Exceeded 5 (0x5) Fault #BR No Invalid Opcode 6 (0x6) Fault #UD No Device Not Available 7 (0x7) Fault #NM No Double Fault 8 (0x8) Abort #DF Yes (Zero) Coprocessor Segment Overrun 9 (0x9) Fault - No Invalid TSS 10 (0xA) Fault #TS Yes Segment Not Present 11 (0xB) Fault #NP Yes Stack-Segment Fault 12 (0xC) Fault #SS Yes General Protection Fault 13 (0xD) Fault #GP Yes Page Fault 14 (0xE) Fault #PF Yes Reserved 15 (0xF) - - No x87 Floating-Point Exception 16 (0x10) Fault #MF No Alignment Check 17 (0x11) Fault #AC Yes Machine Check 18 (0x12) Abort #MC No SIMD Floating-Point Exception 19 (0x13) Fault #XM/#XF No Virtualization Exception 20 (0x14) Fault #VE No Reserved 21-29 (0x15-0x1D) - - No Security Exception 30 (0x1E) - #SX Yes Reserved 31 (0x1F) - - No Triple Fault - - - No FPU Error Interrupt IRQ 13 Interrupt #FERR No Exceptions Faults Divide-by-zero Error The Divide-by-zero Error occurs when dividing any number by 0 using the DIV or IDIV instruction. Many OS developers use this exception to test whether their exception handling code wor
Reserved | I/D | RSVD| U/S | W/R osdev page fault | P | +-----+-...-+-----+-----+-----+-----+-----+-----+ P: When set, the fault was caused by gpf not handled opcode from v86 a protection violation.When not set, it was caused by a non-present page. W/R: When set, write access caused the http://wiki.osdev.org/Exceptions fault; otherwise read access. U/S: When set, the fault occurred in user mode; otherwise in supervisor mode. RSVD: When set, one or more page directory entries contain reserved bits which are set to 1.This only applies when the PSE http://wiki.osdev.org/Page_Fault or PAE flags in CR4 are set to 1. I/D: When set, the fault was caused by an instruction fetch.This only applies when the No-Execute bit is supported and enabled. The CR2 register contains the 32-bit linear address that caused the fault. Retrieved from "http://wiki.osdev.org/index.php?title=Page_Fault&oldid=19311" Category: Interrupts Personal tools Log in Namespaces Page Discussion Variants Views Read View source View history Actions Search Navigation Main Page Forums FAQ OS Projects Random page About This site Joining Editing help Recent changes Toolbox What links here Related changes Special pages Printable version Permanent link This page was last modified on 2 June 2016, at 12:47. This page has been accessed 11,234 times. Privacy policy About OSDev Wiki Disclaimers
are: use of an invalid selector, use of a selector for which the program has insufficient privileges, use of an offset outside the limits of a segment, execution of an illegal opcode, or division by zero. The DPMI host distinguishes between exceptions http://www.delorie.com/djgpp/doc/dpmi/ch4.5.html and external hardware interrupts or software interrupts. Handlers for exceptions can only be installed http://www.cirosantilli.com/x86-paging/ with Int 31H Functions 0203H, 0212H, or 0213H. If the client does not install a handler for a particular exception, or installs a handler but chains to the host's default handler, the host reflects the exception as a real mode interrupt for exceptions 0,1,2,3,4,5, and 7. The default behavior of exceptions 6 and 8-1FH is to terminate the general protection client (some hosts may decide that they have to terminate the VM because the fault came from real mode code or it is in a non-terminatable state). Function 0203H was defined in DPMI version 0.9 and continues to be supported in DPMI version 1.0 for compatibility reasons. Exception handlers installed with Function 0203H are only called for exceptions that occur in protected mode. All exceptions are examined by the DPMI host. The host general protection fault processes any exception that it is responsible for, such as page fault for virtual memory management. These transparent exceptions are never passed to the client exception handlers. All other exceptions become visible exceptions to a client and are passed to the client exception handler (if any) from the DPMI host. The client exception handlers must return with a FAR RETURN, with interrupts disabled on a locked stack, and with SS, (E)SP, CS, and (E)IP registers at the point of exception pushed on the stack. All other registers are unchanged from their contents at the point of exception. The stack frame for 16-bit handlers installed with Function 0203H has the following format: 15 0 +---------------+ | SS | |---------------| 0EH | SP | |---------------| 0CH | Flags | |---------------| 0AH | CS | |---------------| 08H | IP | |---------------| 06H | Error Code | |---------------| 04H | Return CS | |---------------| 02H | Return IP | |---------------| 00H <-- SS:SP The stack frame for 32-bit handlers installed with Function 0203H has the following format: 31 15 0 +---------------+---------------| | Reserved | SS | +---------------+---------------| 1CH | ESP | |-------------------------------| 18H | EFLAGS | |---------------+---------------| 14H | Reserved | CS | |---------------+---------------| 10H | EIP | |-------------------------------| 0CH | Error Code | |---------------+---------------| 08H | | Return C
my Stack Overflow answer. Sample code Intel manual Application Hardware implementation Paging vs segmentation Example: simplified single-level paging scheme Page tables Page table entries Address translation in single-level scheme Page fault Simplifications Example: multi-level paging scheme Address translation in multi-level scheme 64-bit architectures PAE PSE PAE and PSE page table schemes TLB Basic operation Replacement policy CAM Invalidating entries Linux kernel usage Kernel vs process memory layout Process memory layout Source tree Memory management unit Other architectures Bibliography Sample code Minimal example: https://github.com/cirosantilli/x86-bare-metal-examples/blob/5c672f73884a487414b3e21bd9e579c67cd77621/paging.S Like everything else in programming, the only way to really understand this is to play with minimal examples. What makes this a “hard” subject is that the minimal example is large because you need to make your own small OS. Intel manual Although it is impossible to understand without examples in mind, try to get familiar with the manuals as soon as possible. Intel describes paging in the Intel Manual Volume 3 System Programming Guide - 325384-056US September 2015 Chapter 4 “Paging”. Specially interesting is Figure 4-4 “Formats of CR3 and Paging-Structure Entries with 32-Bit Paging”, which gives the key data structures. Application Paging makes it easier to compile and run two programs at the same time on a single computer. For example, when you compile two programs, the compiler does not know if they are going to be running at the same time or not. So nothing prevents it from using the same RAM address, say, 0x1234, to store a global variable. But if two programs use the same address and run at the same time, this is obviously going to break them! Paging solves this problem beautifully by adding one degree of indirection: (logical) ------------> (physical) paging Compilers don’t need to worry about other programs: they just use simple logical addresses. As far as programs are concerned, they think they can use any address between 0 and 4GB