End Module Error
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Error (10170): Verilog Hdl Syntax Error At Near Text "="; Expecting ".", Or "("
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Verilog Syntax Error Near Endmodule
you, helping each other. Join them; it only takes a minute: Sign up Unknown verilog error 'expecting “endmodule”' up vote 3 down vote favorite In verilog I have an error that I can't get past. this is verilog expecting the first bit of the code then the last bit module Decoder(op,funct,aluop,mwr,mreg,mrd,alusrc,regdst,regwr,btype); input[5:0] op,funct; output[2:0] aluop; output[1:0] btype; output mwr,mreg,mrd,alusrc,regdst,regwr; wire aluop,mwr,mreg,mrd,alusrc,regdst,regwr,btype; case(op) 6'b000000: begin case(funct) 6'b001010: assign aluop = 3'b010; 6'b001100: assign aluop = 3'b111; 6'b010001: assign aluop = 3'b011; default: assign aluop = 3'b000; endcase assign btype = 2'b00; assign mwr = 1'b0; assign mreg = 1'b0; assign mrd = 1'b0; assign alusrc = 1'b0; assign regdst = 1'b1; assign regwr = 1'b1; expecting 'endmodule' found 'for' end ... default: begin assign aluop = 3'b000; assign mwr = 0; assign mreg = 0; assign mrd = 0; assign alusrc = 0; assign btype = 2'b00; assign regdst = 0; assign regwr = 0; end endcase endmodule it keeps giving me the following errors Error (10170): Verilog HDL syntax error at Decoder.v(7) near text "case"; expecting "endmodule" Error (10170): Verilog HDL syntax error at Decoder.v(14) near text "6"; expecting "endmodule" It also does this at every end statement and default and endcase I have no idea why it's doing this, I'm fairly new to verilog. thanks in advance verilog share|improve this question asked May 4 '12 at 5:53 Alex Mousavi 1031311 add a comment| 2 Answers 2 active oldest votes up vote 6 down vote accepted I believe you're only allowed to use a case statement or if/else inside of an always block. I'm not sure why your error message doesn't say something a little more helpful, but that is likely to be the problem. Try rewriting your code like the following: //change wire types to reg type always @* begin case (op) 6'b000000: begin aluop = 3'b000 end ... endcase end share|improve this answer answered May 4 '12 at 7:25 Tim 28.1k76095 The decoder in theory shouldn't use registers though. Will it really matter though if they are regis
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Error 10170 Quartus
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Object On Left-hand Side Of Assignment Must Have A Variable Data Type
Overflow Community Stack Overflow is a community of 4.7 million programmers, just like you, helping each other. Join them; it only takes a minute: Sign up I'm getting an expecting 'endmodule' error in Verilog http://stackoverflow.com/questions/10443368/unknown-verilog-error-expecting-endmodule up vote 0 down vote favorite I've looked over my code, and I see nothing wrong. Here's the specific error, any help appreciated: ERROR:HDLCompilers:26 - "myGates.v" line 33 expecting 'endmodule', found 'input' Analysis of file <"myGates.prj"> failed. module myGates( input sw0, input sw1, input sw2, input sw3, output ld0, output ld1, output ld2, output ld3, output ld7 ); input sw0, sw1, sw2, sw3; output ld0, ld1, ld2, http://stackoverflow.com/questions/29474952/im-getting-an-expecting-endmodule-error-in-verilog ld3, ld7; wire w1, w2; assign ld0 = sw0; assign ld1 = sw1; assign ld2 = sw2; assign ld3 = sw3; and u1 (w1, sw0, sw1); and u2 (w2, sw2, sw3); and u3 (ld7, w1, w2); endmodule verilog share|improve this question asked Apr 6 '15 at 16:09 user3857154 383 add a comment| 1 Answer 1 active oldest votes up vote 2 down vote accepted You are mixing ANSI and non-ANSI header styles. You have to pick one ANSI : Supported since IEEE std 1364-2001 (RECOMMENDED): module myGates( // direction, type, range, and name here input sw0, sw1, sw2, sw3, output ld0, ld1, ld2, ld3, output ld7 ); wire w1, w2; // internal wire/reg // your code ... endmodule Non-ANSI : Mandated in IEEE std 1364-1995 and pre-IEEE. Since IEEE std 1364-2001 this is supported for backward comparability. module myGates( // name only here sw0, sw1, sw2, sw3, ld0, ld1, ld2, ld3, ld7 ); input sw0, sw1, sw2, sw3; // direction & range here output ld0, ld1, ld2, ld3; output ld7; // <- if 'reg' type, then type & range here wire w1, w2; // internal wire/reg // your code ... endmodule share|improve this answer answered Apr 6 '15 at
here for a quick overview of the site Help Center Detailed answers to any questions you might have Meta Discuss the workings and policies of this site About Us Learn more about Stack Overflow the company Business Learn http://stackoverflow.com/questions/23204078/endmodule-error-while-compiling more about hiring developers or posting ads with us Stack Overflow Questions Jobs Documentation Tags Users Badges Ask Question x Dismiss Join the Stack Overflow Community Stack Overflow is a community of 4.7 million programmers, just like you, helping each other. Join them; it only takes a minute: Sign up endmodule error while compiling up vote 0 down vote favorite I am trying to code a memory test algorithm in Verilog. This code is a syntax error part of it. I am trying to write a state machine to set the read select signal. I am getting compilation errors like : near "endcase": syntax error, unexpected endcase. Any help would be appreciated. This is my code: module testarch (q, clk, reset, data_in, r_s); input clk; input reset; output [0:2] q; output data_in; output r_s; reg data_in; reg [0:2] q; // address location reg [0:2] state; // state machine reg r_s; integer done=0; reg end module error [0:1] l=0; always@(posedge clk or posedge reset or state) begin //1 if(reset) begin state <= 1; q<=0; end else begin case(state) 1 : //first four stages begin repeat (8) begin @(posedge clk) begin while (!done) begin case(l) 0: begin q<=q; end 1: begin q<=q; end 2: begin q<=q; end 3: begin q<=q+1; done<=1; end endcase end end @(negedge clk) begin while (!done) begin case(l) 0: begin l<=l+1; r_s<=1; end 1: begin l<=l+1; r_s<=1; data_in<=1; end 2: begin l<=l+1; r_s<=1; data_in<=0; end 3: begin l<=l+1; r_s<=1; data_in<=0; end endcase end end end // end repeat endcase end //end else //end //end always endmodule verilog system-verilog share|improve this question edited Apr 28 '15 at 20:28 toolic 30.4k43468 asked Apr 21 '14 at 19:06 Hitch 125 add a comment| 1 Answer 1 active oldest votes up vote 2 down vote accepted You have a missing "end" between the end that is labelled with the comment "end repeat" and the "endcase" (because there's a "begin" before the repeat that needs to be closed before you can close the case). This isn't entirely obvious because the indentation style you're using is confusing. I reindented the code so I could see what is going on, and I suggest using a style closer to this one in future because it does make it easier to find problems like this: module testarch (q, clk,