Following Verilog Source Has Syntax Error
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Verilog Syntax Error Token Is Always
as follows: module register( input clk, e, input [7:0]in, output reg [7:0]out ); always@(posedge clk or posedge e) begin if(e == 1) out <= in; else out <= out; end endmodule When I compile everything, I get the following errors: Error-[USVSNM] Unsupported System Verilog construct register.v, 1 lm2 Found 'module' keyword inside a module before the 'endmodule'. Nested modules are not supported. Error-[SE] Syntax error Following verilog source has syntax error : "register.v", 2: token is 'input' verilog unexpected token input clk, e, ^ I'm scratching my head on this one. I only see module declared once, and I don't see anything wrong with my syntax. Any help is appreciated! verilog system-verilog hdl share|improve this question asked May 13 '14 at 16:19 anthozep 8413 You say SystemVerilog, but you are not using an SV constructs. register is written in Verilog-2001. –Greg May 13 '14 at 16:48 add a comment| 1 Answer 1 active oldest votes up vote 2 down vote accepted I'm guessing that somewhere in your design there is something like the following: module upper_module; // ... `include "register.v" // ... endmoudle This would create a nested module. To fix it, move the `include line above module or below endmodule. Technically nested modules are part of SystemVerilog (see IEEE Std 1800-2005 § 19.6 Nested modules & IEEE Std 1800-2012 § 23.4 Nested modules), however may vendors have not implemented this feature. FYI: or posedge e shouldn't be there. Synchronous logic should be a edged clock and zero to two async resets, where the async reset assigns the flop(s) to a content. share|improve this answer edited May 13 '14 at 16:46 answered May 13 '14 at 16:39 Greg 9,97451939 That was it! It was included in another module above the module declaration, but that module was included in another module, hence the issue. Thank you! Also
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Forum List Topic List New Topic Search Register User List Log In Very simple Verilog array error, fresh eyes appreciated. Author: AlephOne (Guest) Posted on: 2012-04-24 00:48 Rate this post 0 ▲ useful ▼ not useful I'm designing a single-cycle CPU in Verilog, compiling using Chronologic VCS v. 2006 on a Sun Linux server. Below is a trimmed up version of the code that's giving me trouble, and the exact verbatim code below is still giving me the error: Parsing design file 'test.v' Error-[SE] Syntax error "test.v", 5: token is '[' reg_array[0] = 134; ^ 1 error CPU time: 0 seconds to compile module regfile; reg [31:0] reg_array[0:31]; //array of 32-bit registers reg_array[0] = 134; reg_array[2] = 854; reg_array[6] = 223; reg_array[7] = 4878; reg_array[8] = 9855; reg_array[10] = 2; reg_array[20] = 0; reg_array[21] = 1; reg_array[31] = 5555; endmodule I assume it is a painfully simple solution but I am too tired and stupid to find it right now. Fresh eyes appreciated. Thanks all! Report post Edit Move Thread sperren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote Re: Very simple Verilog array error, fresh eyes appreciated. Author: Lothar Miller (lkmiller) (Moderator) Posted on: 2012-04-24 08:51 Rate this post 0 ▲ useful ▼ not useful > I assume it is a painfully simple solution I usually do VHDL, but what about the keywords initial or always? At least this compiles fine: module regfile; reg [31:0] reg_array[0:31]; //array of 32-bit registers initial begin reg_array[0] = 134; : : reg_array[31] = 5555; end endmodule Report post Edit Delete Quote selected text Reply Reply with quote Forum List Topic List New Topic Search Register User List Log In Watch this topic | Disable multi-page view Reply Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in. Rules — please read before posting Post long source code as attachment, not in the text Posting advertisements is forbidden. Formatting options [c]C code[/c] [avrasm]AVR assembler code[/avrasm] [vhdl]VHDL code[/vhdl] [code]code in other languages, ASCII drawings[/code] [math]formula (LaTeX syntax)[/math] Name: E-mail address (not visible): Subject: Searching for similar topics... [hide] Attachment: Bild automatisch verkleinern, falls nötig Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one. Text: Forum List Topic List New Topic Search Register User List Log In webmaster@em