Parse Error Unexpected Case Vhdl
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Syntax Error Near Case Vhdl
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Vhdl Syntax Error Near End
just like you, helping each other. Join them; it only takes a minute: Sign up Cases throwing unexpected when up vote 1 down vote favorite I'm making a statemachine in VHDL. My case is throwing an unexpected
Vhdl Else If
when error case state IS --state 1 A WHEN s0=> --Half step if(FULL = '0' AND RIGHT = '1') then state <= s1; else if (RIGHT = '0') then state <= s7; end if; --Full step if (FULL = '1' AND RIGHT = '1') then state <= s2; else if (RIGHT = '0') then state <= s6; end if; --State 2 A&B WHEN s1=> if(RIGHT = '0') then state <= s0; else if (RIGHT = '1') then state <= s2; end if; However, when running a syntax check with xilinx ISE I'm greeted with a ERROR:HDLParsers:164 Line 72. parse error, unexpected WHEN, expecting END This happens 8 times in total. What am I doing wrong? case vhdl state-machines fpga xilinx share|improve this question asked Sep 17 '13 at 9:41 Samyn 110210 1 Which is line 72? –Dave Moore Sep 17 '13 at 9:43 add a comment| 2 Answers 2 active oldest votes up vote 2 down vote accepted The if and end if are not balanced, so you will have to close the if with some more end if, or use elsif instead of else if. You write: if ... then ... else if ... then ... end if; Even through your indentation shows this like balanced, it is not, since the right indentation would be: if ... then ... else if ... then ... end if; Then it is clear that the if and end if are not balance. If you use elsif you can write it as: if ... then ... elsif ... then ... end if; share|improve this answer answered Sep 17 '13 at 10:25 Morten Zilmer 10.6k2930 add a comment| up vote 0 down vote Once you have done the correction suggested by @MortenZdk, you need to also consid
here for a quick overview of the site Help Center Detailed answers to any questions you might have Meta Discuss the workings and policies of this site About Us Learn more about Stack Overflow the company Business Learn more about hiring developers or posting ads with us Stack Overflow Questions Jobs Documentation Tags Users Badges Ask Question x Dismiss Join the Stack Overflow Community Stack Overflow is a community of 6.2 million programmers, just like you, helping each other. Join them; it only takes a minute: Sign up Unexpected if vhdl up vote 2 down vote favorite This error has been mindfucking me for long, I don't http://stackoverflow.com/questions/18846403/cases-throwing-unexpected-when know what to do. I get the same error in other codes, but this one is a simple one, so maybe it's easier to find out what's the problem. It's a frequency selector, if the switch (clau) is on, the frequency changes. library IEEE; use IEEE.numeric_bit.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- http://stackoverflow.com/questions/13211789/unexpected-if-vhdl any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity selector_frequencia is Port ( unHz : in bit ; centHz : in bit ; Clock : out bit; clau: in bit); end selector_frequencia; architecture Behavioral of selector_frequencia is begin if (clau = "0") then Clock <= unHz; else Clock <= centHz; end if; end Behavioral; And the error I get is this one: ERROR:HDLParsers:164 - "C:/Documents and Settings/Administrador/Escritorio/practica_digital/practica_digital/selector_frequencia.vhdl" Line 23. parse error, unexpected IF Thank you. vhdl share|improve this question asked Nov 3 '12 at 17:43 user1796876 112 1 BTW, even if you get this working, this design will result in random-length runt clock pulses if your select signal clau is ever changed while the circuit is in operation. This flaw makes any synchronous logic using the resultant clock completely unreliable. –wjl Nov 4 '12 at 0:48 add a comment| 3 Answers 3 active oldest votes up vote 3 down vote I'm not really an expert in VHDL but I believe you should use the if statement inside a process: architecture Behavioral of selector_frequencia is begin fqsel:PROCESS(unHz , centHz , Clock , clau) BEGIN if (clau = '0') then Clock <= unHz; else Clock <= centHz; end if; END PROCESS fqsel; end Behavioral; share|improve this answer edited Nov 4 '12 at 5:03 answered Nov 3
tour help Tour Start here for a quick overview of the site Help Center Detailed answers to any questions you might have Meta Discuss the workings and policies of http://electronics.stackexchange.com/questions/107037/syntax-error-in-vhdl-code this site About Us Learn more about Stack Overflow the company Business Learn http://electronics.stackexchange.com/questions/115419/signal-assignment-in-out-process more about hiring developers or posting ads with us Electrical Engineering Questions Tags Users Badges Unanswered Ask Question _ Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. Join them; it only takes a minute: Sign up Here's how it works: syntax error Anybody can ask a question Anybody can answer The best answers are voted up and rise to the top Syntax error in VHDL code up vote 1 down vote favorite I'm trying to implement controller module as a FSM using VHDL, below is the code entity controller is Port ( reset : in STD_LOGIC; clk : in STD_LOGIC; ring_k_1 : in STD_LOGIC; b_n syntax error near : in STD_LOGIC_vector(3 downto 0); start : in STD_LOGIC; STOP : out STD_LOGIC; LOAD_CMD : out STD_LOGIC; ADD_CMD : out STD_LOGIC; BYPASS_CMD : out STD_LOGIC); end controller; architecture Behavioral of controller is --declare states type state_typ is (IDLE, INIT, TEST, ADD, BYPASS); signal state : state_typ; begin process(reset,clk) variable i : STD_LOGIC := '0'; begin if reset = '0' then state <= IDLE; else if clk'event and clk = '1' then case state is when IDLE => if START = '1' then state <= INIT; else state <= IDLE; end if; when INIT => state <= TEST; when TEST => if ring_k_1 = '1' then state <= IDLE; else if ring_k_1 = '0' and b_n(i) = '0' then state <= BYPASS; i <= i+1; else if (ring = '0' and b_n(i) = '1') then state <= ADD; i <= i+1; end if; end case; --Syntax error near "case". end if; --end for the clock event end process; --Syntax error near "process". STOP <= '1' when state = IDLE else '0'; ADD_CMD <= '1' when state = ADD else '0'; BYPASS_CMD <= '1' when state = BYPASS else '0'; LOA
tour help Tour Start here for a quick overview of the site Help Center Detailed answers to any questions you might have Meta Discuss the workings and policies of this site About Us Learn more about Stack Overflow the company Business Learn more about hiring developers or posting ads with us Electrical Engineering Questions Tags Users Badges Unanswered Ask Question _ Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. Join them; it only takes a minute: Sign up Here's how it works: Anybody can ask a question Anybody can answer The best answers are voted up and rise to the top Signal assignment in/out process up vote 1 down vote favorite Inside_process : process(clk) begin if clk='1' and clk'event then signal1 <= signalin; signal2 <= signal1; end if; Out_signal <= signal1 and (not signal2); end process Inside_process; end rtl; VS Outside_process : process(clk) begin if clk='1' and clk'event then signal1 <= signalin; signal2 <= signal1; end if; end process Outside_process; Out_signal <= signal1 and (not signal2); end rtl; I see in some codes signal assignments are made inside processes and sometimes just a bit before end rtl; in this case rtl is architecture. Sometimes many signals are assigned outside process sometimes many. In above example I get no synthesis error and the my circuit works with both versions. So I don't understand what is the difference between them also some signals can't be assigned in the process they have to be outside and they make difference! Why can some be assigned in process why some not? Why sometimes it doesn't make difference? Also how frequently are the signals assigned outside the process, every rising clock edge? Every 5th rising clock edge? How is it decided? What is the use of assigning a signal outside the processes? If I'm going to assign a signal outside a process I usually do it before end rtl; (the last line). I noticed it doesn't hurt doing this between 2 processes as well, so doesn't have to be just before the last line, can be in the middle as well. If I should give an example signal assignment in process which gives an error : d3 <= r4 when (sn(3)='1') else d2; Full code of error line Error msg: parse error, unexpected WHEN, expecting SEMICOLON. There is a semicolon actually. But when this line is taken out of the process, it works. I don't understand how, if someone can enlighten me I would be glad. Also in VHDL shall I declare processes uppercase letters,