Device Error Cn0 Core Instruction Parity
a Support Case Contact Support Policies and Warranties Documentation Products BIG-IP LTM BIG-IP AAM BIG-IP AFM BIG-IP Analytics BIG-IP APM BIG-IP ASM BIG-IP DNS BIG-IP GTM BIG-IP Link Controller BIG-IP PEM BIG-IQ Centralized Management FirePass Mobile & App Store Apps F5 iWorkflow DDoS Hybrid Defender SSL Orchestrator View all Products Architectures Amazon Web Services Services Consulting Training Certification Support Programs Need Additional Help? Open a Support Case Contact Support Policies and Warranties Downloads BIG-IP 12.x BIG-IP 11.x BIG-IP 10.x BIG-IP 9.x BIG-IQ Enterprise Manager 3.x FirePass Platform / EUD See All Downloads AskF5 Home SOL10062 Applies To: Show Versions BIG-IP LTM 12.1.1, 12.1.0, 12.0.0, 11.6.1, 11.6.0, 11.5.4, 11.5.3, 11.5.2, 11.5.1, 11.5.0, 11.4.1, 11.4.0, 11.3.0, 11.2.1, 11.2.0, 11.1.0, 11.0.0, 10.2.4, 10.2.3, 10.2.2, 10.2.1, 10.2.0, 10.1.0, 10.0.1, 10.0.0, 9.6.1, 9.6.0, 9.4.8, 9.4.7, 9.4.6, 9.4.5, 9.4.4, 9.4.3, 9.4.2, 9.4.1, 9.4.0, 9.3.1, 9.3.0, 9.2.5, 9.2.4, 9.2.3, 9.2.2, 9.2.0, 9.1.3, 9.1.2, 9.1.1, 9.1.0 BIG-IP AAM 12.1.1, 12.1.0, 12.0.0, 11.6.1, 11.6.0, 11.5.4, 11.5.3, 11.5.2, 11.5.1, 11.5.0, 11.4.1, 11.4.0 BIG-IP AFM 12.1.1, 12.1.0, 12.0.0, 11.6.1, 11.6.0, 11.5.4, 11.5.3, 11.5.2, 11.5.1, 11.5.0, 11.4.1, 11.4.0, 11.3.0 BIG-IP APM 12.1.1, 12.1.0, 12.0.0, 11.6.1, 11.6.0, 11.5.4, 11.5.3, 11.5.2, 11.5.1, 11.5.0, 11.4.1, 11.4.0, 11.3.0, 11.2.1, 11.2.0, 11.1.0, 11.0.0, 10.2.4, 10.2.3, 10.2.2, 10.2.1, 10.2.0, 10.1.0 BIG-IP ASM 12.1.1, 12.1.0, 12.0.0, 11.6.1, 11.6.0, 11.5.4, 11.5.3, 11.5.2, 11.5.1, 11.5.0, 11.4.1, 11.4.0, 11.3.0, 11.2.1, 11.2.0, 11.1.0, 11.0.0, 10.2.4, 10.2.3, 10.2.2, 10.2.1, 10.2.0, 10.1.0, 10.0.1, 10.0.0, 9.4.8, 9.4.7, 9.4.6, 9.4.5, 9.4.4, 9.4.3, 9.4.2, 9.4.1, 9.4.0, 9.3.1, 9.3.0, 9.2.5, 9.2.4, 9.2.3, 9.2.2, 9.2.0 BIG-IP DNS 12.1.1, 12.1.0, 12.0.0 BIG-IP GTM 11.6.1, 11.6.0, 11.5.4, 11.5.3, 11.5.2, 11.5.1, 11.5.0, 11.4.1, 11.4.0, 11.3.0, 11.2.1, 11.2.0, 11.1.0, 11.0.0, 10.2.4, 10.2.3, 10.2.2, 10.2.1, 10.2.0, 10.1.0, 10.0.1, 10.0.0, 9.4.8, 9.4.7, 9.4.6, 9.4.5, 9.4.4, 9.4.3, 9.4.2, 9.4.1, 9.4.0, 9.3.1, 9.3.0, 9.2.5, 9.2.4, 9.2.3, 9.2.2 BIG-IP Link Controller 12.1.1, 12.1.0, 12.0.0, 11.6.1, 11.6.0, 11.5.4, 11.5.3, 11.5.2, 11.5.1, 11.5.0, 11.4.1, 11.4.0, 11.3.0, 11.2.1, 11.2.0, 11.1.0, 11.0.0, 10.2.4, 10.2.3, 10.2.2, 10.2.1, 10.2.0, 10.1.0, 10.0.1, 10.0.0, 9.4.8, 9.4.7, 9.4.6, 9.4.5, 9.4.4, 9.4.3, 9.4.2, 9.4.1, 9.4.0, 9.3.1, 9.3.0, 9.2.5, 9.2.4, 9.2.3, 9.2.2 BIG-IP PEM 12.1.1, 12.1.0, 12.0.0, 11.6.1, 11.6.0, 11.5.4, 11.5.3, 11.5.2, 11.5.1, 11.5.0, 11.4.1, 11.4.0, 11.3.0 BIG-IP PSM 11.4.1, 11.4.0, 11.3.0, 11.2.1, 11.2.0, 11.1.0, 11.0.0, 10.2.4, 10.2.
✉ Feedback Skip to Main Content Skip to Footer Navigation Sorry, your browser is not supported. We recommend upgrading your browser. We have done our best to make all the documentation and resources available on old versions of Internet Explorer, but vector image support and the layout may not be optimal. Technical documentation is available as a PDF Download. JavaScript seems to be disabled in your browser. You must have JavaScript enabled in your browser to utilize the functionality of this website. Home Embedded Software Development Linux & Open-Source Academia Graphics & Multimedia Development SoC Design http://support.f5.com/kb/en-us/solutions/public/10000/000/sol10062.html High Performance Computing Products Support Technologies Main Menu Products Support Technologies ARM Cortex-A53 MPCore Processor Technical Reference Manual Revision: r0p4 Developer Documentation ARM Cortex-A53 MPCore Processor Technical Reference Manual Revision: r0p4 Preface 1. Introduction 1.1. About the Cortex-A53 processor 1.2. Compliance 1.2.1. ARM architecture 1.2.2. Interconnect architecture 1.2.3. Generic Interrupt Controller architecture 1.2.4. Generic Timer architecture 1.2.5. Debug architecture 1.2.6. Embedded Trace Macrocell architecture 1.3. https://developer.arm.com/docs/ddi0500/f/a-signal-descriptions/a5-generic-interrupt-controller-signals Features 1.4. Interfaces 1.5. Implementation options 1.5.1. Processor configuration 1.6. Test features 1.7. Product documentation and design flow 1.7.1. Documentation 1.7.2. Design flow 1.8. Product revisions 2. Functional Description 2.1. About the Cortex-A53 processor functions 2.1.1. Instruction Fetch Unit 2.1.2. Data Processing Unit 2.1.3. Advanced SIMD and Floating-point Extension 2.1.4. Cryptography Extension 2.1.5. Translation Lookaside Buffer 2.1.6. Data side memory system 2.1.7. L2 memory system 2.1.8. Cache protection 2.1.9. Debug and trace 2.2. Interfaces 2.2.1. Master memory interface 2.2.2. Accelerator Coherency Port 2.2.3. External debug interface 2.2.4. Trace interface 2.2.5. CTI 2.2.6. DFT 2.2.7. MBIST 2.2.8. Q-channel 2.3. Clocking and resets 2.3.1. Clocks 2.3.2. Input synchronization 2.3.3. Resets 2.4. Power management 2.4.1. Power domains 2.4.2. Power modes 2.4.3. Event communication using WFE or SEV 2.4.4. Communication to the Power Management Controller 3. Programmers Model 3.1. About the programmers model 3.1.1. Advanced SIMD and Floating-point support 3.1.2. Memory model 3.1.3. Jazelle implementation 3.1.4. Modes of operation 3.2. ARMv8-A architecture concepts 3.2.1. Execution state 3.2.2. Exception levels 3.2.3. Security state 3.2.4. Rules for changing execution state 3.2.5. Stack pointer selection 3.2.6. ARMv8 security model 3.2.7. Instruction set state 3.2.8. AArch32 execution modes 4.