Error - V2ks
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file 'mult_test.v'Parsing design file 'mult.v'Error-[V2KS] Verilog 2000 IEEE 1364-2000 syntax used. Please compile with+v2kto support this constructComma separated sensitivity lists."mult.v", 50Parsing design file 'ALU_struct.v'1 errorWhat does that mean? Is there a way to get around it?Thanks,Xiao Joel VanLaven 2003-09-25 23:41:48 UTC PermalinkRaw Message My guess is that you are using incorrect syntax in the:always @(a or b or c) portion of your code.like maybe you are doing:always @(a,b,c)Since none http://stackoverflow.com/questions/33748438/errors-in-benchmark-code of the code I have ever used or ever seen has given thiserror, I might be wrong. I'm simply basing my guess on the text of theerror.-- JoelPost by Xiao LiangHi,I was trying to complile mult_test.v, mult.v and ALU_struct.v, makefileParsing design file 'mult_test.v'Parsing design file 'mult.v'Error-[V2KS] Verilog 2000 IEEE http://umich.eecs.class.470.narkive.com/d6nwBeZk/compiler-error 1364-2000 syntax used. Please compile with+v2kto support this constructComma separated sensitivity lists."mult.v", 50Parsing design file 'ALU_struct.v'1 errorWhat does that mean? Is there a way to get around it?Thanks,Xiao Joel VanLaven 2003-09-26 00:18:34 UTC PermalinkRaw Message Oh yeah, also I think the error is on line 50 of mult.v and I haveverified that my guess will generate the same error.-- JoelPost by Xiao LiangHi,I was trying to complile mult_test.v, mult.v and ALU_struct.v, makefileParsing design file 'mult_test.v'Parsing design file 'mult.v'Error-[V2KS] Verilog 2000 IEEE 1364-2000 syntax used. Please compile with+v2kto support this constructComma separated sensitivity lists."mult.v", 50Parsing design file 'ALU_struct.v'1 errorWhat does that mean? Is there a way to get around it?Thanks,Xiao 2 Replies 102 Views Switch to linear view Disable enhanced parsing Permalink to this page Thread Navigation Xiao Liang 2003-09-25 23:22:56 UTC Joel VanLaven 2003-09-25 23:41:48 UTC Joel VanLaven 2003-09-26 00:18:34 UTC about - legalese Loading...
so I was following this tutorial to do verilog simulations in iverilog. http://iverilog.wikia.com/wiki/GTKWAVE Both counter.v and counter_tb.v compiled fine and I was able to get the wave forms like it says with http://boardreader.com/thread/Error_when_compiling_with_VCS_6wkocX76pd.html GTKWave. Now I tried to compile the same .v files with VCS and this was the error I ended up getting. Code: Error-[V2KS] Verilog 2000 IEEE 1364-2000 syntax... Top contributing authors: Name Posts tenso 5 user's latest post: Error when compiling with VCS Published (2015-04-18 21:37:00) Originally Posted by dpaul You have again not posted the entire cmd. Did you use the option -debug_all which is necessary to create a simv executable? Then error - it is time for you look into the VCS Reference Manual and see what options who need and why is it failing. I copy-pasted the entire compilation in my post. There is nothing better I can do. yes to the bolded here is what i ran HTML Code: vcs -debug_all +v2k counter.v counter_tb.v This is... dpaul 3 user's latest post: Error when compiling with VCS Published (2015-04-18 09:14:00) Originally Posted by tenso error - v2ks there seems to be an error when compiling that results in simv not being an executable. This is the error message I get. You have again not posted the entire cmd. Did you use the option -debug_all which is necessary to create a simv executable? Originally Posted by tenso I was hoping someone could point me in the right direction. Then it is time for you look into the VCS Reference Manual and see what options who... ads-ee 2 user's latest post: Error when compiling with VCS Published (2015-04-20 17:15:00) Just search on the melf_386 brings up the following: https://bugzilla.redhat.com/show_bug.cgi?id=902318 yuhiub90 1 user's latest post: Error when compiling with VCS Published (2015-04-10 14:48:00) Add -R option to your compilation. VCS will execute the simulation automatically. Related threads on "Forum for Electronics": What caused errors when compiling U-Boot? What caused errors when compiling U-Boot? VHDL - Fatal error when get input process VHDL - Fatal error when get input process ERROR when load PVS after finish installation in Cadence ERROR when load PVS after finish installation in Cadence [Moved] Error when analyzing simulation of HFSS 11 [Moved] Error when analyzing simulation of HFSS 11 Error when i compile sd card library on pic18f8722 mcu... Error when i compile sd card library on pic18f8722 mcu using microC C
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