Make Build Error 2
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Make Error 2 Linux
Join the Stack Overflow Community Stack Overflow is a community of 6.2 million programmers, just like you, helping each other. Join them; it only make all error 2 takes a minute: Sign up Make / gcc cryptic error 2: how to have more information? up vote 2 down vote favorite I have this C++ project which compiles using a Makefile, and sometimes when (my guess) there are some gcc error 2 missing includes, I get a cryptic "error 2" message and the make process stops. I suspect the missing includes because this is the third times it happens when I included a non-existent header file. It looks like this: ---- Build tmp/foo.o ---- ---- Build tmp/bar.o ---- ---- Build tmp/toto.o ---- ---- Build tmp/tata.o ---- make: *** [build_Project] Error 2 This is driving me nuts, because even using verbose commands (where each g++ invocation is showed), I can't see anything. I expected
Makefile Error 2 Qt
the guy to throw up some erroneous messages like "can't find header X" or "undefined reference to Y", but there's nothing. My compiling options for gcc are -O0 -Wall -Werror -Wno-write-strings -fno-rtti -fno-exceptions, if this helps. Ah, and we use the Makefile trick of including dependencies: ifneq ($(strip $(DEPENDS)),) ifneq ($(MAKECMDGOALS),clean) -include $(DEPENDS) endif endif ( see here and here for more information ) Although this is documented stuff, I suspect my problem has something to do with this dependencies inclusion. If you already stumbled on this issue, feel free to comment on this... Thanks in advance. edit: Okay, after a bit of playing, suppressing the - in front of -include $(DEPENDS) gives me some more info (the makefile does stop on the missing included file). make[1]: *** No rule to make target « foo.h », necessary for « tmp/bar.d ». Stop. Now the drawback is that when I launch make for the first time, I get a missing bar.d file message for each dependency file that should be included (which was why we put the - in the first place). Any solution? c++ gcc dependencies makefile share|improve this question edited Mar 22 '11 at 14:40 asked Mar 22 '11 at 10:55 Gui13 5,30353370 1 I think we need to see more of the makefile e.g. how you call gcc- and I tend to show the command compiling for this sort of reason –Mark Mar 22 '11 at 1
to fix them. Sometimes make errors are not fatal, especially in the presence of a - prefix on a recipe line, or the -k command line option. Errors that gcc error 1 are fatal are prefixed with the string ***. Error messages are all either prefixed make error log with the name of the program (usually ‘make’), or, if the error is found in a makefile, the name of
Make 1 Entering Directory
the file and line number containing the problem. In the table below, these common prefixes are left off. ‘[foo] Error NN’ ‘[foo] signal description’ These errors are not really make errors at all. They http://stackoverflow.com/questions/5390081/make-gcc-cryptic-error-2-how-to-have-more-information mean that a program that make invoked as part of a recipe returned a non-0 error code (‘Error NN’), which make interprets as failure, or it exited in some other abnormal fashion (with a signal of some type). See Errors in Recipes. If no *** is attached to the message, then the sub-process failed but the rule in the makefile was prefixed with the - special character, so make https://www.gnu.org/s/make/manual/html_node/Error-Messages.html ignored the error. ‘missing separator. Stop.’ ‘missing separator (did you mean TAB instead of 8 spaces?). Stop.’ This means that make could not understand much of anything about the makefile line it just read. GNU make looks for various separators (:, =, recipe prefix characters, etc.) to indicate what kind of line it’s parsing. This message means it couldn’t find a valid one. One of the most common reasons for this message is that you (or perhaps your oh-so-helpful editor, as is the case with many MS-Windows editors) have attempted to indent your recipe lines with spaces instead of a tab character. In this case, make will use the second form of the error above. Remember that every line in the recipe must begin with a tab character (unless you set .RECIPEPREFIX; see Special Variables). Eight spaces do not count. See Rule Syntax. ‘recipe commences before first target. Stop.’ ‘missing rule before recipe. Stop.’ This means the first thing in the makefile seems to be part of a recipe: it begins with a recipe prefix character and doesn’t appear to be a legal make directive (such as a variable assignment). Recipes must always be associated with a target. The second form is gene
communities company blog Stack Exchange Inbox Reputation and Badges sign up log in tour help Tour Start here for a quick overview of the site Help Center Detailed answers to any questions you might have Meta Discuss the workings and policies of this http://askubuntu.com/questions/620182/error-when-using-command-make site About Us Learn more about Stack Overflow the company Business Learn more about http://help.eclipse.org/neon/topic/org.eclipse.cdt.doc.user/concepts/cdt_c_makefile.htm hiring developers or posting ads with us Ask Ubuntu Questions Tags Users Badges Unanswered Ask Question _ Ask Ubuntu is a question and answer site for Ubuntu users and developers. Join them; it only takes a minute: Sign up Here's how it works: Anybody can ask a question Anybody can answer The best error 2 answers are voted up and rise to the top Error when using command 'make' up vote 0 down vote favorite I get error whenever I'm trying to 'make' file, I did this before I typed 'make': tar xjf xarchiver-0.5.4.tar.bz2 cd ./xarchiver-0.5.4 ./configure Configure command: thomas@thomas-pc:~/Downloads/xarchiver-0.5.4$ ./configure checking build system type... x86_64-unknown-linux-gnu checking host system type... x86_64-unknown-linux-gnu checking target system type... x86_64-unknown-linux-gnu checking for a BSD-compatible install... make build error /usr/bin/install -c checking whether build environment is sane... yes checking for gawk... no checking for mawk... mawk checking whether make sets $(MAKE)... yes checking whether to enable maintainer-specific portions of Makefiles... no checking for style of include used by make... GNU checking for gcc... gcc checking for C compiler default output file name... a.out checking whether the C compiler works... yes checking whether we are cross compiling... no checking for suffix of executables... checking for suffix of object files... o checking whether we are using the GNU C compiler... yes checking whether gcc accepts -g... yes checking for gcc option to accept ISO C89... none needed checking dependency style of gcc... gcc3 checking how to run the C preprocessor... gcc -E checking for grep that handles long lines and -e... /bin/grep checking for egrep... /bin/grep -E checking for AIX... no checking for library containing strerror... none required checking for ANSI C header files... yes checking for sys/types.h... yes checking for sys/stat.h... yes checking for stdlib.h... yes checking for string.h... yes checking for memory.h... yes checking for strings.h... yes checking for inttypes.h... yes checking for stdint.h... yes checking for unistd.h... yes checking minix/config.h usability... no checking minix/config.h presence...
build-order dependencies. The CDT can generate a makefile for you, such projects are called Managed Make projects. Some projects, known as Standard Make projects, allow you to define your own makefile. Sample Makefile # A sample Makefile # This Makefile demonstrates and explains # Make Macros, Macro Expansions, # Rules, Targets, Dependencies, Commands, Goals # Artificial Targets, Pattern Rule, Dependency Rule. # Comments start with a # and go to the end of the line. # Here is a simple Make Macro. LINK_TARGET = test_me.exe # Here is a Make Macro that uses the backslash to extend to multiple lines. # This allows quick modification of more object files. OBJS = \ Test1.o \ Test2.o \ Main.o # Here is a Make Macro defined by two Macro Expansions. # A Macro Expansion may be treated as a textual replacement of the Make Macro. # Macro Expansions are introduced with $ and enclosed in (parentheses). REBUILDABLES = $(OBJS) $(LINK_TARGET) # Make Macros do not need to be defined before their Macro Expansions, # but they normally should be defined before they appear in any Rules. # Consequently Make Macros often appear first in a Makefile. # Here is a simple Rule (used for "cleaning" your build environment). # It has a Target named "clean" (left of the colon ":" on the first line), # no Dependencies (right of the colon), # and two Commands (indented by tabs on the lines that follow). # The space before the colon is not required but added here for clarity. clean : rm -f $(REBUILDABLES) echo Clean done # There are two standard Targets your Makefile should probably have: # "all" and "clean", because they are often command-line Goals. # Also, these are both typically Artificial Targets, because they don't typically # correspond to real files named "all" or "clean". # The rule for "all" is used to incrementally build your system. # It does this by expressing a dependency on the results of that system, # which in turn have their own rules and dependencies. all : $(LINK_TARGET) echo All done # There is no required order to the list of rules as they appear in the Makefile