Error No Design Loaded Modelsim
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The Design Unit Was Not Found
Documentation Tags Users Badges Ask Question x Dismiss Join the Stack Overflow Community Stack Overflow is a community of 4.7 million programmers, modelsim design unit was not found just like you, helping each other. Join them; it only takes a minute: Sign up ModelSim Error Loading Design up vote 0 down vote favorite I'm designing a Master-Slave D Flip Flop implementation in ModelSim. After compiling https://www.altera.com/support/support-resources/knowledge-base/solutions/rd09222000_9765.html (Compile > Compile All), I'm typing vsim into the console, and the only error thrown is # vsim # Start time: [time] # Error loading design Is there any way of having vsim be more verbose with what is going wrong? Or, alternately, could someone tell me what I'm doing wrong? For reference, my code is below: methods.v module dFlipFlop( D, Clk, En, Q ); input D, Clk, En; output Q; reg Q; always http://stackoverflow.com/questions/29544794/modelsim-error-loading-design @ (posedge Clk) if(~En) begin Q <= 1'b0; end else begin Q <= D; end endmodule module masterSlaveDFF( D, Clk, En, Q ); input D, Clk, En; output Q; wire Y, inClk; assign inClk = ~Clk; dFlipFlop first (.D(D), .Clk(Clk), .En(En), .Q(Y)); dFlipFlop second (.D(Y), .Clk(inClk), .En(En), .Q(Q)); endmodule dflipflop.v (My Testbench) `include "methods.v" module masterSlaveTest(); reg D, Clk, En, Q; initial begin $monitor(D, Clk, En, Q); D = 1; Clk = 1; En = 0; #5 $finish; end always begin #5 Clk = ~Clk; end endmodule verilog modelsim share|improve this question asked Apr 9 '15 at 17:09 Aeolingamenfel 1,697621 Did you instruct the compiler where to find the included file? Some simulators use +incdir+/some/dir, but I do not use ModelSim. –toolic Apr 9 '15 at 17:38 Yeah I've tried specifically invoking my Test Bench file too, to no avail. –Aeolingamenfel Apr 9 '15 at 17:42 When I paste all your code into a single file, it compiles and runs with Cadence's simulator. So, your code looks good. –toolic Apr 9 '15 at 18:01 Ahh. I figured it out. It wasn't my code or the configuration, though those were good suggestions for sure. It was the student license. I'm gonna resolve it myself ha. –Aeolingamenfel Apr 9 '15 at 18:12 Tha
Forum Device and Tools Related Quartus II and EDA Tools Discussion no design loaded with MODELSIM If this is your first visit, be sure to check out the FAQ by clicking the link above. http://www.alteraforum.com/forum/showthread.php?t=22588 You may have to register before you can post: click the register link above https://groups.google.com/d/topic/modelsim-pe-student-edition/B07gfdS6h50 to proceed. To start viewing messages, select the forum that you want to visit from the selection below. Results 1 to 1 of 1 Thread: no design loaded with MODELSIM Thread Tools Show Printable Version Email this Page… Subscribe to this Thread… Search Thread Advanced Search Display Linear Mode Switch to Hybrid Mode Switch to error loading Threaded Mode April 23rd, 2010,05:25 AM #1 BMX View Profile View Forum Posts Altera Scholar Join Date Apr 2010 Posts 24 Rep Power 1 no design loaded with MODELSIM Hi everyone, My design is compiled succssfully with quartus II, but when Iwant to execute Macro from Tools menu in Modelsim, there is no design loaded and I got this msg in the command prompt: # ** Error: too many nested evaluations error loading design (infinite loop?) .... # invoked from within # "source $script" Can anyone help me? Reply With Quote Quick Navigation Quartus II and EDA Tools Discussion Top Site Areas Settings Private Messages Subscriptions Who's Online Search Forums Forums Home Forums General General Altera Discussion Altera Forum Website Related Altera Wiki Device and Tools Related FPGA, Hardcopy, and CPLD Discussion SoC Discussion SoC Device Discussion SoC Linux Other SoC Operating Systems SoC Baremetal and Hardware Libraries SoC Bootloading Quartus II and EDA Tools Discussion Embedded Design Suite (EDS) OpenCL Nios Forum General Discussion General Discussion Forum General Software Forum Nios II C-to-Hardware Acceleration Altera Wiki Operating Systems Linux Forum Innovateasia Contest - Linux for Nios II ecos Forum MicroC/OS-II Forum Nucleus Forum Coding Questions Verilog and System Verilog VHDL C and C++ IP and Dev Kit Related IP Discussion DSP Builder and DSP IPs Development Kit Related SoC Development Kits University Program Shared Material Shared Material « Counter.. Having problems adding? Please help! | Quartus 9.0 SP1 program crashes » Similar Threads ModelSim-Altera Error loading design By travis.miller in forum Quartus II and EDA Tools Discussion Replies: 4 Last Post: September 17th, 2010, 11:12 PM Target request failed: No symbol table is loaded. By Benjamin Dobell in forum General Software
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