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Join the Stack Overflow Community Stack Overflow is a community of 4.7 million programmers, just like you, helping each other. Join them; it only modelsim student license takes a minute: Sign up ModelSim Error Loading Design up vote 0 down vote favorite I'm designing a Master-Slave D Flip Flop implementation in ModelSim. After compiling (Compile > Compile All), I'm typing vsim into the console, and the only https://www.altera.com/support/support-resources/knowledge-base/solutions/rd09222000_9765.html error thrown is # vsim # Start time: [time] # Error loading design Is there any way of having vsim be more verbose with what is going wrong? Or, alternately, could someone tell me what I'm doing wrong? For reference, my code is below: methods.v module dFlipFlop( D, Clk, En, Q ); input D, Clk, En; output Q; reg Q; always @ (posedge Clk) if(~En) begin Q <= 1'b0; end else begin Q <= D; end endmodule module masterSlaveDFF( D, Clk, http://stackoverflow.com/questions/29544794/modelsim-error-loading-design En, Q ); input D, Clk, En; output Q; wire Y, inClk; assign inClk = ~Clk; dFlipFlop first (.D(D), .Clk(Clk), .En(En), .Q(Y)); dFlipFlop second (.D(Y), .Clk(inClk), .En(En), .Q(Q)); endmodule dflipflop.v (My Testbench) `include "methods.v" module masterSlaveTest(); reg D, Clk, En, Q; initial begin $monitor(D, Clk, En, Q); D = 1; Clk = 1; En = 0; #5 $finish; end always begin #5 Clk = ~Clk; end endmodule verilog modelsim share|improve this question asked Apr 9 '15 at 17:09 Aeolingamenfel 1,697621 Did you instruct the compiler where to find the included file? Some simulators use +incdir+/some/dir, but I do not use ModelSim. –toolic Apr 9 '15 at 17:38 Yeah I've tried specifically invoking my Test Bench file too, to no avail. –Aeolingamenfel Apr 9 '15 at 17:42 When I paste all your code into a single file, it compiles and runs with Cadence's simulator. So, your code looks good. –toolic Apr 9 '15 at 18:01 Ahh. I figured it out. It wasn't my code or the configuration, though those were good suggestions for sure. It was the student license. I'm gonna resolve it myself ha. –Aeolingamenfel Apr 9 '15 at 18:12 Thank you for the help, though, @toolic. –Aeolingamenfel Apr 9 '15 at 18:17 add a comment| 2 Answers 2 active oldest votes up vote 0 down vote If your code compiles, and directly invoking a test bench doesn't work, aka via
Forum Device and Tools Related Quartus II and EDA Tools Discussion ModelSim-Altera Error loading design If this is your first visit, be http://www.alteraforum.com/forum/showthread.php?t=20213 sure to check out the FAQ by clicking the link above. You http://www.xilinx.com/itp/xilinx10/help/platform_studio/ps_c_sim_loading_modelsim_design.htm may have to register before you can post: click the register link above to proceed. To start viewing messages, select the forum that you want to visit from the selection below. Results 1 to 5 of 5 Thread: ModelSim-Altera Error loading design Thread Tools Show Printable error loading Version Email this Page… Subscribe to this Thread… Search Thread Advanced Search Display Linear Mode Switch to Hybrid Mode Switch to Threaded Mode December 15th, 2009,03:35 PM #1 travis.miller View Profile View Forum Posts Altera Beginner Join Date Dec 2009 Posts 2 Rep Power 1 ModelSim-Altera Error loading design Hello, This is my first time using ModelSim and error loading design writing testbenches, so this may sound like a silly problem. But I am having problems simulating my project on ModelSim from Quartus II. Here is the testbench I have written up for the project: module test_tgen; reg CLK_IN; reg reset; reg IN_4ms; reg OUT_4ms; reg OUT_1ms; reg OUT_20KHZ; reg LOST_SINK; timing_gen_block mytiming_gen(reset, IN_4ms, CLK_IN, OUT_4ms, OUT_1ms, OUT_20KHZ, LOST_SINK); initial // Clock generator begin CLK_IN = 0; forever #8 CLK_IN = !CLK_IN; end initial // Test stimulus begin reset = 0; IN_4ms = 1; #5 reset = 1; #250 IN_4ms = 0; end initial $monitor($stime,, reset,, IN_4ms,, CLK_IN); endmodule Now this compiles just fine. But when I try to simulate it in ModelSim from Quartus II by selecting Tools > Run EDA Simulation Tool > EDA RTL Simulation, I get the following output in ModelSim: # Reading C:/altera/91/modelsim_ase/tcl/vsim/pref.tcl # do Timing_Gen_block_run_msim_rtl_verilog.do # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Copying C:\altera\91\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini # Modifying modelsim.ini # ** Warning: Copied C:\altera\91\modelsim_ase\
to initialize.Loading VHDL DesignsIf your top level created by EDK was in VHDL, load the design using:ModelSim> vsim system_confThis command loads the configuration. The simulator uses the design and all of the parameters specified in the configuration. As a result, you will have all of the memory blocks initialized with the appropriate data.If you do not have any data to put into memory blocks, you can use the following command to load the design only:ModelSim> vsim systemLoading Verilog DesignsIf your top level created by EDK was in Verilog, load the design using:ModelSim> vsim system system_conf glblThis loads the system module, which loads the module containing the parameter definitions that initialize the memory blocks in your system and loads the glbl module.If you do not have any data to put into memory blocks, use the following command to load only the system and the glbl modules:ModelSim> vsim system glblNote The Verilog files written by EDK employ the uselib directive to load simulation libraries. Still, you only need to use -Lf for user-defined libraries.When using any Virtex™-5 Hard IP, such as PowerPC, MGT, and PCIe, it is required to load the secureip library. This is a Verilog library which can be loaded wit the -L secureip switch. The secureip library is available for ModelSim versions 6.3d and higher.See AlsoSimulating in ModelSimCompiling Simulation Models for ModelSim DesignsProviding Stimulus to a ModelSim DesignRunning a ModelSim DesignCopyright © 2008, Xilinx Inc. All rights reserved.