Modelsim Error Loading Design Verilog
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List Topic List New Topic Search Register User List Log In Error loading design (Modelsim student version) Author: Keltuzad (Guest) Posted on: 2009-10-09 error loading design modelsim altera 18:08 Rate this post 0 ▲ useful ▼ not useful Hi
The Design Unit Was Not Found
@ all, Im working with the student version of Modelsim, I have dowloaded the latest version (6.5b) and
Modelsim Student License
the licence and copied it to the root folder(C:\dev\Modeltech_pe_edu_6.5b). Now to the problem: Im using "vsim -voptargs=+acc work.tdm_bert_tb" as my run command. My only error report is: #Error loading
Error (vsim-3170) Could Not Find
design Due to the limited content of the error msg I have difficulties finding a solution. What have I already done: I have reinstalled Modelsim + licence with Administrator rights, tried running it with different -commands e.g. vsim -optargs work.tdm_bert_tb, vsim work.tdm_bert_tb (none). I only recieve the above mentoinened error. Any suggestions are welcome. Thanks in advance. Kel. 2009-10-12 modelsim error log 14:45: Moved by Admin Report post Edit Move Thread sperren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote Re: Error loading design (Modelsim student version) Author: guest (Guest) Posted on: 2009-10-09 19:53 Rate this post 0 ▲ useful ▼ not useful did you compile your designfiles/tb into the work lib using vlib and vcom? Report post Edit Delete Quote selected text Reply Reply with quote Re: Error loading design (Modelsim student version) Author: Kel (Guest) Posted on: 2009-10-10 13:40 Rate this post 0 ▲ useful ▼ not useful hi, yes all files including the testbench are compiled. Report post Edit Delete Quote selected text Reply Reply with quote Re: Error loading design (Modelsim student version) Author: Christian R. (supachris) Posted on: 2009-10-10 14:31 Rate this post 0 ▲ useful ▼ not useful In the most cases the error is shown many lines obove the "Error loading design" Message. Search the blue lines for "Fatal : ..." or so. Report post Edit Delete Quote selected text Reply Reply with quo
here for a quick overview of the site Help Center Detailed answers to any questions you might have Meta Discuss the workings error loading design pausing macro execution and policies of this site About Us Learn more about Stack Overflow questasim error loading design the company Business Learn more about hiring developers or posting ads with us Stack Overflow Questions Jobs Documentation modelsim design unit was not found Tags Users Badges Ask Question x Dismiss Join the Stack Overflow Community Stack Overflow is a community of 6.2 million programmers, just like you, helping each other. Join them; http://embdev.net/topic/error-loading-design-modelsim-student-version it only takes a minute: Sign up Error loading design modelsim PE student edition 10.4 up vote 1 down vote favorite I'm creating a new project which i called alpha,then i create a new file test.vhd. library ieee; use ieee.std_logic_1164.all; entity d_latch is port( data_in:in std_logic; data_out:out std_logic; enable:in std_logic); end d_latch; architecture beh of d_latch is begin process(data_in,enable) begin http://stackoverflow.com/questions/28357845/error-loading-design-modelsim-pe-student-edition-10-4 if(enable <= '1') then data_out <= data_in; end if; end process; end beh; I add test.vhd to the project alpha then i compile the file.After that i simulate->start simulate then i check [+] work library then the module presented in it,but an error's message appears Error loading design vhdl modelsim share|improve this question asked Feb 6 '15 at 2:57 hmidi slim 612 1 You better create a testbench (so with an empty entity) where you add your d_latch component into it. Compile that testbench and then run it. –vermaete Feb 6 '15 at 7:43 add a comment| 2 Answers 2 active oldest votes up vote 1 down vote First edit the if statement to get the correct results : if(enable <= '1') must be if(enable = '1') I simulated your code and no errors found. Simulation results was correct. Just open modelsim software, click file and change directory (for example to the address of test.vhd file) Then compile test.vhd and simulate it. Sometimes you should close modelsim and do the same stages again, because the library directo
Forum Device and Tools Related Quartus II and EDA Tools Discussion ModelSim-Altera Error loading design If this is your first visit, be http://www.alteraforum.com/forum/showthread.php?t=20213 sure to check out the FAQ by clicking the link above. You http://search.edaboard.com/error-loading-design-modelsim.html may have to register before you can post: click the register link above to proceed. To start viewing messages, select the forum that you want to visit from the selection below. Results 1 to 5 of 5 Thread: ModelSim-Altera Error loading design Thread Tools Show Printable error loading Version Email this Page… Subscribe to this Thread… Search Thread Advanced Search Display Linear Mode Switch to Hybrid Mode Switch to Threaded Mode December 15th, 2009,03:35 PM #1 travis.miller View Profile View Forum Posts Altera Beginner Join Date Dec 2009 Posts 2 Rep Power 1 ModelSim-Altera Error loading design Hello, This is my first time using ModelSim and error loading design writing testbenches, so this may sound like a silly problem. But I am having problems simulating my project on ModelSim from Quartus II. Here is the testbench I have written up for the project: module test_tgen; reg CLK_IN; reg reset; reg IN_4ms; reg OUT_4ms; reg OUT_1ms; reg OUT_20KHZ; reg LOST_SINK; timing_gen_block mytiming_gen(reset, IN_4ms, CLK_IN, OUT_4ms, OUT_1ms, OUT_20KHZ, LOST_SINK); initial // Clock generator begin CLK_IN = 0; forever #8 CLK_IN = !CLK_IN; end initial // Test stimulus begin reset = 0; IN_4ms = 1; #5 reset = 1; #250 IN_4ms = 0; end initial $monitor($stime,, reset,, IN_4ms,, CLK_IN); endmodule Now this compiles just fine. But when I try to simulate it in ModelSim from Quartus II by selecting Tools > Run EDA Simulation Tool > EDA RTL Simulation, I get the following output in ModelSim: # Reading C:/altera/91/modelsim_ase/tcl/vsim/pref.tcl # do Timing_Gen_block_run_msim_rtl_verilog.do # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Copying C:\altera\91\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini # Modifying modelsim.ini # ** Warning: Copied C:\altera\91\modelsim_ase\win32aloem/../
edaboard.com: Error Loading Design Modelsim Verror 3033 the design unit was not found HI friends, can you please Help me, how to solve the following error in modelsim loading work.iu_verilog1 ** error: (vsim-3033) /mnt/iscsi/Users/ee5113/zxv764/vsim/leon2-1.0.30-xst/leon/iu_verilog1.v(31): Instantiation of 'iu_syn_updated' failed. The design unit was not found. Region: (...) PLD, SPLD, GAL, CPLD, FPGA Design :: 10-18-2014 17:14 :: abu9022 :: Replies: 4 :: Views: 772 Error Loading Design - ModelSim PE Student Version Hi, I have created a do file and able to compile successfully.. But when I give vsim top_instanct_name, it is showing "error loading design" error loading design # error: error loading design # Pausing (...) Software Links :: 05-07-2013 09:32 :: sktarun :: Replies: 0 :: Views: 46 ALU32bit in MIPS 32bits single cyle When I simulate this file, modelsim showed that: "error loading design". But i don't know how to fix it. Could you help me! THankss I attached 2 file below.89781 PLD, SPLD, GAL, CPLD, FPGA Design :: 04-21-2013 21:05 :: nghiatran2129 :: Replies: 0 :: Views: 526 Help me solve an error loading design in Modelsim Hi friends, While simulating program in modelsim i am getting error loading design. Currently i am using student version. Can u suggest me the how to solve the problem. ASIC Design Methodologies and Tools (Digital) :: 08-07-2012 06:11 :: ashok.cheepati :: Replies: 1 :: Views: 1803 anyone using 'fedora Electornic Lab' software Hi guys, my first preference was to use modelsim PE student edition for learning purposes but there is some problem with their student license and I keep getting "error loading design" message when I try to simulate. Now in a website I read about fedora electronic lab. Any body using this software? And whats their (...) ASIC Design Methodologies and Tools (Digital) :: 06-13-2010 03:39 :: verilog_coder :: Replies: 0 :: Views: 941 problem with glbl.v modelsim while using secure ips Hi, I am trying to simulate a design using modelsim 6.6b PE. The design contains one secure ip. The compilation is successful but while loading the design following error is displayed " Fatal: attempting to load -nodebug design unit." nodebug designs (...) PLD, SPLD, GAL, CPLD, FPGA Design :: 06-06-2010 08:33 :: subhashcjj :: Replies: 0 :: Views: 1258 ModelSIM error "Failed to find 'glbl' in hierarchical n