Modelsim Error Loading Design Vhdl
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List Topic List New Topic Search Register User List Log In Error loading design (Modelsim student version) Author: Keltuzad error loading design modelsim altera (Guest) Posted on: 2009-10-09 18:08 Rate this post 0 ▲ useful
Error Loading Design Questasim
▼ not useful Hi @ all, Im working with the student version of Modelsim, I have dowloaded
Error Loading Design Modelsim Verilog
the latest version (6.5b) and the licence and copied it to the root folder(C:\dev\Modeltech_pe_edu_6.5b). Now to the problem: Im using "vsim -voptargs=+acc work.tdm_bert_tb" as my run command.
Modelsim Student License
My only error report is: #Error loading design Due to the limited content of the error msg I have difficulties finding a solution. What have I already done: I have reinstalled Modelsim + licence with Administrator rights, tried running it with different -commands e.g. vsim -optargs work.tdm_bert_tb, vsim work.tdm_bert_tb (none). I only recieve the above the design unit was not found mentoinened error. Any suggestions are welcome. Thanks in advance. Kel. 2009-10-12 14:45: Moved by Admin Report post Edit Move Thread sperren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote Re: Error loading design (Modelsim student version) Author: guest (Guest) Posted on: 2009-10-09 19:53 Rate this post 0 ▲ useful ▼ not useful did you compile your designfiles/tb into the work lib using vlib and vcom? Report post Edit Delete Quote selected text Reply Reply with quote Re: Error loading design (Modelsim student version) Author: Kel (Guest) Posted on: 2009-10-10 13:40 Rate this post 0 ▲ useful ▼ not useful hi, yes all files including the testbench are compiled. Report post Edit Delete Quote selected text Reply Reply with quote Re: Error loading design (Modelsim student version) Author: Christian R. (supachris) Posted on: 2009-10-10 14:31 Rate this post 0 ▲ useful ▼ not useful In the most cases the error is shown many lines obove the "Error loading design"
here for a quick overview of the site Help Center Detailed answers to any questions you might have Meta Discuss error (vsim-3170) could not find the workings and policies of this site About Us Learn more modelsim error log about Stack Overflow the company Business Learn more about hiring developers or posting ads with us Stack Overflow error loading design pausing macro execution Questions Jobs Documentation Tags Users Badges Ask Question x Dismiss Join the Stack Overflow Community Stack Overflow is a community of 6.2 million programmers, just like you, helping http://embdev.net/topic/error-loading-design-modelsim-student-version each other. Join them; it only takes a minute: Sign up Error loading design modelsim PE student edition 10.4 up vote 1 down vote favorite I'm creating a new project which i called alpha,then i create a new file test.vhd. library ieee; use ieee.std_logic_1164.all; entity d_latch is port( data_in:in std_logic; data_out:out std_logic; enable:in std_logic); end d_latch; architecture beh http://stackoverflow.com/questions/28357845/error-loading-design-modelsim-pe-student-edition-10-4 of d_latch is begin process(data_in,enable) begin if(enable <= '1') then data_out <= data_in; end if; end process; end beh; I add test.vhd to the project alpha then i compile the file.After that i simulate->start simulate then i check [+] work library then the module presented in it,but an error's message appears Error loading design vhdl modelsim share|improve this question asked Feb 6 '15 at 2:57 hmidi slim 612 1 You better create a testbench (so with an empty entity) where you add your d_latch component into it. Compile that testbench and then run it. –vermaete Feb 6 '15 at 7:43 add a comment| 2 Answers 2 active oldest votes up vote 1 down vote First edit the if statement to get the correct results : if(enable <= '1') must be if(enable = '1') I simulated your code and no errors found. Simulation results was correct. Just open modelsim software, click file and change directory (for example to the address of test.vhd file) Then compile test.vhd and simulate it. Sometimes you should
Forum Device and Tools Related Quartus II and EDA Tools Discussion Can't use testbench in Modelsim - error loading design If this is your first visit, be sure to check out the FAQ by clicking the link http://www.alteraforum.com/forum/showthread.php?t=51714 above. You may have to register before you can post: click the register link above to proceed. To start viewing messages, select the forum that you want to visit from the selection below. Results 1 to 5 of 5 Thread: Can't use testbench in Modelsim - error loading design Thread Tools Show Printable Version Email this Page… Subscribe to this Thread… Search Thread Advanced Search Display Linear Mode Switch to Hybrid error loading Mode Switch to Threaded Mode March 12th, 2016,11:25 PM #1 nettek View Profile View Forum Posts Altera Pupil Join Date Mar 2016 Posts 15 Rep Power 1 Can't use testbench in Modelsim - error loading design Hi everyone, First I want to say that I searched all the threads here, and while this is a common problem, I could not figure out how to solve it. I am trying to use a small error loading design testbench I wrote using the Quartus testbench template writer, but I am getting this error: Code: ** Error: (vsim-3170) Could not find 'C:/Users/nettek/QuartusProjects/Final Project - 11.3.16 - par/test/simulation/modelsim/rtl_work.tb_test1'. # # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./Test_run_msim_rtl_vhdl.do PAUSED at line 14 Steps I took: 1. Created a BDF file with two components in it, obviously it has input/output ports and some internal signals. 2. Created an HDL file from the BDF file. Added it to project. Removed the BDF file from project (did not delete it). 3. Created a testbench using the Quartus template writer. 4. Added the VHT file to project. 5. Took to Assignments -> Settings -> EDA tool settings -> Simulation -> Chose compile test bench and chose the VHT file. 6. Tools -> Run simulation tool -> RTL simulation which opened Modelsim. Of course I always made sure to compile whenever I needed to. I don't understand this problem, just two days ago it didn't happen and now it does. What could be the problem? Also, I would appreciate if you could tell me how to test internal signals of a BDF file in Modelsim using a testbench. I know that I can give the signals names, turn the BDF file into a HDL f