Modelsim Error Loading Design
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List Topic List New Topic Search Register User List Log In Error loading design (Modelsim student version) Author: Keltuzad (Guest) Posted on: 2009-10-09 18:08 Rate this
Error Loading Design Questasim
post 0 ▲ useful ▼ not useful Hi @ all, Im working error loading design modelsim verilog with the student version of Modelsim, I have dowloaded the latest version (6.5b) and the licence and copied it modelsim student license to the root folder(C:\dev\Modeltech_pe_edu_6.5b). Now to the problem: Im using "vsim -voptargs=+acc work.tdm_bert_tb" as my run command. My only error report is: #Error loading design Due to the limited content of
The Design Unit Was Not Found
the error msg I have difficulties finding a solution. What have I already done: I have reinstalled Modelsim + licence with Administrator rights, tried running it with different -commands e.g. vsim -optargs work.tdm_bert_tb, vsim work.tdm_bert_tb (none). I only recieve the above mentoinened error. Any suggestions are welcome. Thanks in advance. Kel. 2009-10-12 14:45: Moved by Admin Report post Edit Move Thread sperren
Error (vsim-3170) Could Not Find
Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote Re: Error loading design (Modelsim student version) Author: guest (Guest) Posted on: 2009-10-09 19:53 Rate this post 0 ▲ useful ▼ not useful did you compile your designfiles/tb into the work lib using vlib and vcom? Report post Edit Delete Quote selected text Reply Reply with quote Re: Error loading design (Modelsim student version) Author: Kel (Guest) Posted on: 2009-10-10 13:40 Rate this post 0 ▲ useful ▼ not useful hi, yes all files including the testbench are compiled. Report post Edit Delete Quote selected text Reply Reply with quote Re: Error loading design (Modelsim student version) Author: Christian R. (supachris) Posted on: 2009-10-10 14:31 Rate this post 0 ▲ useful ▼ not useful In the most cases the error is shown many lines obove the "Error loading design" Message. Search the blue lines for "Fatal : ..." or so. Report post Edit Delete Quote selected text Reply Reply with quote Re: Error loading design (Modelsim student version) Author: Kel (Guest) Posted on: 2009-10-12 12:43 Rate this post 0 ▲ useful
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Error Loading Design Pausing Macro Execution
Tags Users Badges Ask Question x Dismiss Join the Stack Overflow Community Stack Overflow is a community of 6.2 million programmers, just modelsim design unit was not found like you, helping each other. Join them; it only takes a minute: Sign up ModelSim Error Loading Design up vote 0 down vote favorite I'm designing a Master-Slave D Flip Flop implementation in ModelSim. After compiling (Compile http://embdev.net/topic/error-loading-design-modelsim-student-version > Compile All), I'm typing vsim into the console, and the only error thrown is # vsim # Start time: [time] # Error loading design Is there any way of having vsim be more verbose with what is going wrong? Or, alternately, could someone tell me what I'm doing wrong? For reference, my code is below: methods.v module dFlipFlop( D, Clk, En, Q ); input D, Clk, En; output Q; reg Q; always @ (posedge http://stackoverflow.com/questions/29544794/modelsim-error-loading-design Clk) if(~En) begin Q <= 1'b0; end else begin Q <= D; end endmodule module masterSlaveDFF( D, Clk, En, Q ); input D, Clk, En; output Q; wire Y, inClk; assign inClk = ~Clk; dFlipFlop first (.D(D), .Clk(Clk), .En(En), .Q(Y)); dFlipFlop second (.D(Y), .Clk(inClk), .En(En), .Q(Q)); endmodule dflipflop.v (My Testbench) `include "methods.v" module masterSlaveTest(); reg D, Clk, En, Q; initial begin $monitor(D, Clk, En, Q); D = 1; Clk = 1; En = 0; #5 $finish; end always begin #5 Clk = ~Clk; end endmodule verilog modelsim share|improve this question asked Apr 9 '15 at 17:09 Aeolingamenfel 1,707621 Did you instruct the compiler where to find the included file? Some simulators use +incdir+/some/dir, but I do not use ModelSim. –toolic Apr 9 '15 at 17:38 Yeah I've tried specifically invoking my Test Bench file too, to no avail. –Aeolingamenfel Apr 9 '15 at 17:42 When I paste all your code into a single file, it compiles and runs with Cadence's simulator. So, your code looks good. –toolic Apr 9 '15 at 18:01 Ahh. I figured it out. It wasn't my code or the configuration, though those were good suggestions for sure. It was the student license. I'm gonna resolve it myself ha. –Aeolingamenfel Apr 9 '15 at 18:12 Thank you for the h
Forum Device and Tools Related Quartus II and EDA Tools Discussion Can't use testbench in Modelsim - error loading design If this is your first visit, be sure to check out the FAQ by clicking the link above. http://www.alteraforum.com/forum/showthread.php?t=51714 You may have to register before you can post: click the register link above https://groups.google.com/d/topic/modelsim-pe-student-edition/B07gfdS6h50 to proceed. To start viewing messages, select the forum that you want to visit from the selection below. Results 1 to 5 of 5 Thread: Can't use testbench in Modelsim - error loading design Thread Tools Show Printable Version Email this Page… Subscribe to this Thread… Search Thread Advanced Search Display Linear Mode Switch to Hybrid Mode Switch error loading to Threaded Mode March 12th, 2016,11:25 PM #1 nettek View Profile View Forum Posts Altera Pupil Join Date Mar 2016 Posts 15 Rep Power 1 Can't use testbench in Modelsim - error loading design Hi everyone, First I want to say that I searched all the threads here, and while this is a common problem, I could not figure out how to solve it. I am trying to use a small testbench I wrote error loading design using the Quartus testbench template writer, but I am getting this error: Code: ** Error: (vsim-3170) Could not find 'C:/Users/nettek/QuartusProjects/Final Project - 11.3.16 - par/test/simulation/modelsim/rtl_work.tb_test1'. # # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./Test_run_msim_rtl_vhdl.do PAUSED at line 14 Steps I took: 1. Created a BDF file with two components in it, obviously it has input/output ports and some internal signals. 2. Created an HDL file from the BDF file. Added it to project. Removed the BDF file from project (did not delete it). 3. Created a testbench using the Quartus template writer. 4. Added the VHT file to project. 5. Took to Assignments -> Settings -> EDA tool settings -> Simulation -> Chose compile test bench and chose the VHT file. 6. Tools -> Run simulation tool -> RTL simulation which opened Modelsim. Of course I always made sure to compile whenever I needed to. I don't understand this problem, just two days ago it didn't happen and now it does. What could be the problem? Also, I would appreciate if you could tell me how to test internal signals of a BDF file in Modelsim using a testbench. I know that I can give the signals names, turn the BDF file into a HDL file and then compile it
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