Modelsim Vsim Error Loading Design
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Business Learn more about hiring developers or posting ads with us Stack Overflow Questions Jobs Documentation Tags Users error loading design pausing macro execution Badges Ask Question x Dismiss Join the Stack Overflow Community Stack Overflow is a community of 6.2 million programmers, just like you, helping each other. Join them; it only takes a https://www.altera.com/support/support-resources/knowledge-base/solutions/rd09222000_9765.html minute: Sign up ModelSim Error Loading Design up vote 0 down vote favorite I'm designing a Master-Slave D Flip Flop implementation in ModelSim. After compiling (Compile > Compile All), I'm typing vsim into the console, and the only error thrown is # vsim # Start time: [time] # Error loading design Is there any way of having vsim be more verbose http://stackoverflow.com/questions/29544794/modelsim-error-loading-design with what is going wrong? Or, alternately, could someone tell me what I'm doing wrong? For reference, my code is below: methods.v module dFlipFlop( D, Clk, En, Q ); input D, Clk, En; output Q; reg Q; always @ (posedge Clk) if(~En) begin Q <= 1'b0; end else begin Q <= D; end endmodule module masterSlaveDFF( D, Clk, En, Q ); input D, Clk, En; output Q; wire Y, inClk; assign inClk = ~Clk; dFlipFlop first (.D(D), .Clk(Clk), .En(En), .Q(Y)); dFlipFlop second (.D(Y), .Clk(inClk), .En(En), .Q(Q)); endmodule dflipflop.v (My Testbench) `include "methods.v" module masterSlaveTest(); reg D, Clk, En, Q; initial begin $monitor(D, Clk, En, Q); D = 1; Clk = 1; En = 0; #5 $finish; end always begin #5 Clk = ~Clk; end endmodule verilog modelsim share|improve this question asked Apr 9 '15 at 17:09 Aeolingamenfel 1,707621 Did you instruct the compiler where to find the included file? Some simulators use +incdir+/some/dir, but I do not use ModelSim. –toolic Apr 9 '15 at 17:38 Yeah I've tried specifically invoking my Test Bench file too, to no avail. –Aeolinga
to initialize.Loading VHDL DesignsIf your top level http://www.xilinx.com/itp/xilinx10/help/platform_studio/ps_c_sim_loading_modelsim_design.htm created by EDK was in VHDL, load the design using:ModelSim> https://forums.xilinx.com/t5/Simulation-and-Verification/ModelSim-PE-Student-Edition-10-3-error/td-p/406997 vsim system_confThis command loads the configuration. The simulator uses the design and all of the parameters specified in the configuration. As a result, you will have all of the memory blocks initialized with the appropriate data.If you error loading do not have any data to put into memory blocks, you can use the following command to load the design only:ModelSim> vsim systemLoading Verilog DesignsIf your top level created by EDK was in Verilog, load the design using:ModelSim> vsim system system_conf glblThis loads the system module, error loading design which loads the module containing the parameter definitions that initialize the memory blocks in your system and loads the glbl module.If you do not have any data to put into memory blocks, use the following command to load only the system and the glbl modules:ModelSim> vsim system glblNote The Verilog files written by EDK employ the uselib directive to load simulation libraries. Still, you only need to use -Lf for user-defined libraries.When using any Virtex™-5 Hard IP, such as PowerPC, MGT, and PCIe, it is required to load the secureip library. This is a Verilog library which can be loaded wit the -L secureip switch. The secureip library is available for ModelSim versions 6.3d and higher.See AlsoSimulating in ModelSimCompiling Simulation Models for ModelSim DesignsProviding Stimulus to a ModelSim DesignRunning a ModelSim DesignCopyright © 2008, Xilinx Inc. All rights reserved.
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